RT9605A Datasheet, PDF (9/12 Pages) Richtek Technology Corporation – Triple-Channel Synchronous-Rectified Buck MOSFET Driver

Preliminary
RT9605A
Application Information
The RT9605A is designed to drive three sets of both high
side and low side N-Channel MOSFET through externally
input PWM control signal. It has power-on protection
function which held UGATE and LGATE low before PV_CC
rising across the threshold voltage. After the initialization,
the PWM signal takes the control. The rising PWM signal
first forces the LGATE turns low then UGATE is allowed
to go high just after a non-overlapping time to avoid shoot-
through. The falling of PWM signal first forces UGATE to
go low. When UGATE and PHASE reach a predetermined
low level, LGATE is allowed to turn high. The non-
overlapping function is also presented between UGATE
and LGATE signal transient.
The PWM signal is acted as "High" if above the rising
threshold and acted as "Low" if below the falling threshold.
Any signal level remaining within the shutdown window is
considered as "tri-state", the output drivers are disabled
and both MOSFET gates are pulled and held low. If the
PWM signal floating, the pin will be kept at 2.1V by the
internal divider and provide the PWM controller with a
recognizable level.
The RT9605A typically operates at frequency of 200kHz
to 300kHz. It shall be noted that to place a 1N4148 or
schottky diode between the PVCC and BOOT pin as
shown in the typical application circuit.
Driving Power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. When V_gs at 12V, the gate draws the
current only few nano-amperes. Thus once the gate has
been driven up to "ON" level, the current could be
negligible.
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large current
to source and sink the gate rapidly. It also needs to switch
drain current on and off with high speed. The required gate
drive currents are calculated as follows.
D1
d1
s1
L
VIN
Cgd1
Cgs1
Igd1 ^Igs1
Ig1
Ig2 ^Igd2
g2
g1
Igs2
Cgd2
d2
D2
Cgs2 s2
V_g1
VPHASE +12V
VOUT
GND
t
V_g2
12V
t
Figure 1. Equivalent Circuit and Associated Waveforms
In Figure 1, the current I_g1 and I_g2 are required to move the
gate up to 12V. The operation consists of charging C_gd
and C_gs. C_gs1 and C_gs2 are the capacitances from gate to
source of the high side and the low side power MOSFETs,
respectively. In general data sheets, the C_gs is referred as
"C_iss" which is the input capacitance. C_gd1 and C_gd2 are
the capacitances from gate to drain of the high side and
the low side power MOSFETs, respectively and referred
to the data sheets as "C_rss" the reverse transfer
capacitance. For example, t_r1 and t_r2 are the rising time of
the high side and the low side power MOSFETs
respectively, the required current I_gs1 and I_gs2 are showed
,
below:
I_gs1
=
C_gs1
dV_g1
dt
=
C_gs1 ×12
t_r1
(1)
I_gs2
= C_gs2
dV_g2
dt
=
C_gs2 ×12
t_r2
(2)
DS9605A-05 August 2007
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