RT9246A Datasheet, PDF (9/16 Pages) Richtek Technology Corporation – Multi-Phase PWM Controller for CPU Core Power Supply

Applications Information
RT9246A is a multi-phase DC/DC controller specifically
designed to deliver high quality power for next generation
CPU. Phase currents are sensed by innovative time-
sharing DCR current sensing technique for channel current
balance, droop tuning, and over current protection. Using
one common GM amplifier for current sensing eliminates
offset errors and linearity variation between GMs. As sub-
milli-ohm-grade inductors are widely used in modern
mother boards, slight mismatch of GM amplifiers offset
and linearity results in considerable current shift between
phases. The time-sharing DCR current sensing technique
is extremely important to guarantee phase current balance
at mass production.
Converter Initialization, Phase Selection, and
Power Good Function
The RT9246A initiates only after two pins are ready: VCC
pin power on reset (POR) and DVD pin is higher than 1V.
VCC POR is to make sure RT9246A is powered by a
voltage for normal work. The rising threshold voltage of
VCC POR is 4.2V typically. At VCC POR, RT9246A checks
PWM3 status to determine phase number of operation.
Pull high PWM3 for two-phase operation. The unused
current sense pin should be connected to GND or left
floating.
DVD is to make sure that ATX12V is ready for companion
MOSFET drivers(RT960X series) to work normally.
Connect a voltage divider from ATX12V to DVD pin as
shown in the Typical Application Circuit. Make sure that
DVD pin voltage is below its threshold voltage before drivers
are ready and above its threshold voltage for minimum
ATX12V during normal operation.
If either one of VCC and DVD is not ready, RT9246A keeps
its PWM outputs high impedance and the companion
drivers turn off both upper and lower MOSFETs. After VCC
and DVD are ready, RT9246A initiates its soft start cycle
as shown in Figure 1. A time-variant internal current source
charges the capacitor connected to SS pin. SS voltage
ramps up piecewise linearly and locks VID_DAC output
with a specified voltage drop. Consequently, V_CORE is built
up according to VID_DAC output. PGOOD output is
tripped to high impedance when V_CORE reaches VID_DAC
RT9246A
output with 1~2ms delay. An SS capacitor about 47nF is
recommend for typical application.
VCC POR and DVD ready
SS
V_CORE
PGOOD
1~2ms 1~2ms 1~2ms
VID Jump
Figure 1. Timming Diagram During Soft Start Interval
Voltage Control
CPU V_CORE voltage is Kelvin sensed by FB and FBRTN
pins and precisely regulated to VID_DAC output by internal
high gain Error Amplifier (EA). The sensed signal is also
used for power good and over voltage function. The typical
OVP trip point is 400mV above VID_DAC output. RT9246A
pulls PWM outputs low and latches up upon OVP trip to
prevent CPU from damaging. It can only restart by resetting
either VCC or DVD pin.
The VID pins are internally pulled high to internal 2.2V
with 13kΩ resistors and are easily interfaced with CPU
VID outputs. The change of VID_DAC output at VID Jump
is also smoothed by capacitor connected to SS pin.
Consequently, V_CORE shifts to its new position smoothly.
DCR Current Sensing
RT9246A adopts an innovative time-sharing DCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance) and load line
regulation as shown in Figure 2. Current sensing amplifier
GM samples and holds voltages V_X across the current
sensing capacitor C_X by turns in a switching cycle.
According to the Basic Circuit Theory, if
LX _{= RX x CX then VX = ILX x RLX}
RLX
Consequently, the sensing current I_X is proportional to
inductor current I_LX and is expressed as :
IX = ^{ILX x RLX}
RCOMM
DS9246A-04 March 2007
www.richtek.com
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