RT9625A Datasheet, PDF (6/14 Pages) Richtek Technology Corporation – Dual-Channel Synchronous Rectified MOSFET Driver

RT9625A
Parameter
EN Input
ENx Rising Threshold
ENx Falling Threshold
PWM Input
Maximum Input Current
PWMx Floating Voltage
PWMx Rising Threshold
PWMx Falling Threshold
Timing
UGATEx Rising Time
UGATEx Falling Time
LGATEx Rising Time
LGATEx Falling Time
Propagation Delay
Output
UGATEx Drive Source
UGATEx Drive Sink
LGATEx Drive Source
LGATEx Drive Sink
Symbol
Test Conditions
Min Typ Max Unit
V_ENH
V_ENL
I_PWM
V_{PWM_fl}
V_{PWM_rth}
V_{PWM_fth}
V_PWMx = 0V or 5V
PWMx = Open
-- 1.3 1.6 V
0.7 1
--
V
-- 160 -- μA
-- 1.8 --
V
2.3 2.8 3.2 V
0.7 1.1 1.4 V
t_UGATEr
t_UGATEf
t_LGATEr
t_LGATEf
t_UGATEpdh
t_UGATEpdl
t_LGATEpdh
t_LGATEpdl
3nF load
3nF load
3nF load
3nF load
V_BOOTx − V_PHASEx = 12V
See Timing Diagram
See Timing Diagram
-- 25 -- ns
-- 12 -- ns
-- 24 -- ns
-- 10 -- ns
-- 30 --
ns
-- 22 --
-- 30 --
ns
--
8
--
R_UGATEsr V_BOOT − V_PHASE = 12V, I_Source = 100mA --
1.7
--
Ω
R_UGATEsk V_BOOT − V_PHASE = 12V, I_Sink = 100mA
-- 1.4 --
Ω
R_LGATEsr
I_Source = 100mA
-- 1.6 --
Ω
R_LGATEsk I_Sink = 100mA
-- 1.1 --
Ω
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
is a registered trademark of Richtek Technology Corporation.
DS9625A-02 September 2012