RT9218B Datasheet, PDF (6/17 Pages) Richtek Technology Corporation – 12V Synchronous Buck PWM DC-DC and Linear Power Controller

RT9218B
Parameter
Symbol
Test Conditions
Error Amplifier (GM)
E/A Transconductance
g_m
Open Loop DC Gain
A_O
Linear Regulator
DRV Driver Source
I_DS
V_DRV = 6V
Reference Voltage
V_REFREG V_CC = 12V
PWM Controller Gate Drivers (V_CC = 12V)
Upper Gate Source
Upper Gate Sink
I_UGATE
R_UGATE
V_BOOT − V_PHASE = 12V
V_UGATE − V_PHASE = 6V
V_BOOT − V_PHASE = 12V
V_UGATE − V_PHASE = 1V
Lower Gate Source
I_LGATE V_CC = 12V, V_LGATE = 6V
Lower Gate Sink
R_LGATE V_CC = 12V, V_LGATE = 1V
Dead Time
T_DT
Protection
FB Under-Voltage Trip
FBL Under-Voltage Trip
OC Current Source
Soft-Start Interval
Power Good
Δ_FBUVT FB Falling
Δ_FBLUVT FB and FBL Falling
I_OC
V_PHASE = 0V
T_SS
Power Good Rising Threshold
V_CC = 12V
Power Good Hysteresis
V_CC = 12V
PG Sink Capability
Power Good Rising Delay
V_CC = 12V, 1mA
V_CC = 12V
Power Good Falling Delay
V_CC = 12V
Min Typ Max Units
-- 0.2 -- ms
-- 90 -- dB
-- 1.4 -- mA
0.792 0.8 0.808 V
0.6 1
--
A
--
4
--
Ω
0.6 1
--
A
--
3
4
Ω
-- -- 100 ns
70 75 80 %
70 75 80 %
-- 40 -- μA
-- 3.5 -- ms
-- 90 --
%
-- 10 --
%
-- 0.2 0.4 V
1
3 10 ms
-- 15 --
us
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
www.richtek.com
6
DS9218B-09 March 2007