RT3606BC Datasheet, PDF (5/72 Pages) Richtek Technology Corporation – Dual Channel PWM Controller

Functional Block Diagram
RT3606BC
IBIAS
RGND
FB
COMP
ISEN1P
ISEN1N
ISEN2P
ISEN2N
ISEN3P
ISEN3N
IMON
RGNDA
FBA
COMPA
ISENA1P
ISENA1N
ISENA2P
ISENA2N
IMONA
MUX
MUX
ADC
ADC
SVID Interface
Configuration Registers
IC1_M
Control Logic
IC2_M
IC3_M
Current Mirror
DAC
IC4_M
2V +
-
IBIASI
VID_M VID_A
DVIDTH_X VR address
DVIDWIDTH_X H/L f_SW ramp
QR_X
DVID SR
QRWIDTH_X _{Disable DVID compensation}
IC1_A
IC2_A
IC3_A
OCS_M
OCS_A
OCS_TH_X _{Decrease GTV/SA ramp (only in 1-phase)}
From Control Logic DVID SR
RSET_X
Zero load-line
DVIDTH_M
ICCMAX_X _Anti-OVS
DAC
DVIDWIDTH_M
OCP_PER_X _{Anti-OVS behavior}
AI gain
Soft-Start & Slew Rate
Control
ERROR
VSET_M AMP
+
-
PSYS function
Offset
Cancellation
PWM
CMP
+
+
-
Current Mirror
+
IC1_M
1/3
-
IB1_M
VREF
+_GM
-
Current Mirror
RSET_M
+
IC2_M
-
IB2_M
Current Mirror
IMON Filter IMONI_M
+
IC3_M
-
IB3_M
+
OCS_TH_M -
OCS_M
From Control Logic
DAC
DVID SR
DVIDTH_A
DVIDWIDTH_A
Soft-Start & Slew Rate
Control
ERROR
VSET_A AMP
+
-
Current Mirror
+
IC1_A
-
IB1_A
Current Mirror
+
IC2_A
-
IB2_A
VREFI
+
-
Offset
Cancellation
1/3
+_GM
-
+
RSET_A
IMON Filter IMONI_A
+
OCS_TH_A -
OCS_A
PWM
CMP
+
-
UVLO
Loop Control Protection
Logic
PS_M PS_A
OV_X/NV_X/
OC_PER_X/OC_SUM_X
PS_M
QRTH_M
QRWIDTH_M
TON
GEN
PWM1
PWM2
Current Balance
Driver
IB1_M IB2_M IB3_M
Anti-OVS
PWMA1
Anti-OVS behavior
PS_A
QRTH_A
QRWIDTH_A
TON
GEN
Current Balance
IB1_A IB2_A
GND
TONSET
PWM3
PVCC
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
BOOTA1
UGATEA1
PHASEA1
LGATEA1
TONSETA
PWMA2
VREF
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
DS3606BC-04 June 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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