RT3606BE Datasheet, PDF (49/70 Pages) Richtek Technology Corporation – Dual Channel PWM Controller

Design Step :
The RT3606BE excel based design tool is available. Users
can contact your Richtek representative to get the
spreadsheet. Three main design procedures for the
RT3606BE design, first step is initial settings, second
step is loop design and the last step is protection settings.
The following design example is to explain the RT3606BE
design procedure :
Input Voltage
No. of Phases
ICCMAX
ICC-DY
ICC-TDC
Load Line
Fast Slew Rate
Max Switching
Frequency
V_CORE Specification
12V
3
90A
69A
68A
2.1m
10mV/s
400kHz
In IMVP8 VRTB Guideline, the output filter requirements
of VRTB specification for desktop platform are :
Output Inductor : 220nH/0.49mΩ
Output Bulk Capacitor : 560μF/2.5V/5mΩ (max) 4 to 5pcs
Output Ceramic Capacitor : 22μF/0805 (19pcs max in
cavity)
Initial Settings :
IBIAS needs to connect a 100kW resistor to ground. A
voltage divider for setting DVD can choose R_{DVD_U} = 510kW
and R_{DVD_L} = 125kW to set V_DVD > 2V, the RT3606BE
enabled.
(1) Loop Design :
On time setting : Using the specification, T_ON is
T_ON

R_TON 
V_IN
4.73p 1.2
 V_DAC
(V_DAC
 1.2)

246n
The on time setting resistor R_TON = 483kΩ
RT3606BE
Current sensor adopts lossless RC filter to sense current
signal in DCR. For getting an expect load transient
waveform, RxCx time constant needs to match Lx /
DCRx per phase. Cx = 1μF is set, then
R_X

L_X
0.47μF  DCR _X
 960
IMON resistor network design : T_L = 25°C, T_R = 50°C
and T_H = 100°C are decided, NTC thermistor =
100kΩ@25°C, β = 4485 and ICCMAX = 90A.
According to the sub-section “Current Loop Design in
Details”, R_IMON1 = 10.66kΩ, R_IMON2 = 16.16kΩ and
R_IMON3 = 1 2.63kΩ can be decided. The R_EQ (25°C) =
24.91kΩ.
Load-line design : 2.1mΩ droop is requirement, because
R_EQ (25°C) has decided, the voltage loop Av gain is also
can be decided by following equation
R_LL

A_I
A_V

1
3

DCR
R_CS

R_EQ
R2
m
R1
Where DCR (25°C) = 0.49mΩ, R_CS = 680Ω and
REQ (25°C) = 24.91kΩ. Hence the A_V = R2 / R1 = 2.85
can be obtained. R1 = 10kΩ usually decided, so R2 =
28.5kΩ.
 Typical compensator design can use the following
equations to design the C1 and C2 values
C1 
R1
1

f_SW
 470pF
C2

C_OUT ESR
R2

98pF
For Intel platform, in order to induce the band width to
enhance transient performance to meet Intel’ s criterion,
the compensator of zero can be designed close to 1/10
of switching frequency.
 SET1 resistor network design : First the ICCMAX is
design as 90A. Next, OCP threshold is designed as
1.5 x ICCMAX. Last, DVID compensation parameters
need to be decided. The DVID_TH can be calculated as
following equation
V_{DVID_TH}
=
LL

C_OUT

dVID
dt
Copyright ©2017 Richtek Technology Corporation. All rights reserved.
DS3606BE-04 June 2017
is a registered trademark of Richtek Technology Corporation.
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