RT9643 Datasheet, PDF (3/17 Pages) Richtek Technology Corporation – 5 Channel ACPI Regulator with Step-Down DC/DC Controller

RT9643
State
S5
S3
S0
S3#I
X
L
H
EN(S5#)
L
H
H
Table 1. While S5àS0àS3
VCC_EN 5VSB_DRV VDDQ VTT_OUT 1.2 OUT
L
L
OFF
OFF
OFF
L
L
ON
OFF
OFF
H
H
ON
ON
ON
3V Dual 5V Dual
ON
OFF
ON +5VSB
OFF +5VMAIN
Start up Sequencing
The VCC pin provides power to all logic and analog control functions of the regulator including : After VCC is above
UVLO, the start-up sequence begins as shown in Figure 1.
5VSB
UVLO
SS
~4V
1.5V
2.5V
2.0V
3V Dual
VDDQ
VTT_OUT/
1.2 OUT
T0
T1
T2 T3 T4 T5 T6 T7
T8
Figure 1
T0 to T3 : After initial power-up, the IC will ignore all logic inputs for a time period (T3-T0) of about :
T3 - T0 = ^{6.5 x CSS}
5μ
The 3V Dual LDO is in regulation. The 3.3V LDO’ s slew rate is limited by the discharge slope of C_SS. If 3V MAIN has
come up prior to this time, the 3V DUAL node will already be pre-charged through the body diode of Q5 (see Figure 1).
T3 to T4 : The IC waits about 100μs before initiating soft-start on VDDQ to allow C_SS time to fully discharged. The IC is
in “SLEEP” or S5 state when EN is low. In S5 only the 3.3V LDO is on. If the IC is in S5 at T4, C_SS will be held to 0V.
T4 to T5 : While First time to enter S0, The IC will start VDDQ only if 5V_MAIN is above its UVLO threshold (5V_MAIN
o.k.) and S3#I is high.
T5 to T7 : After VDDQ is stabilized (when C_SS is above about 1.5V) which will allow the 1.2V LDO and the VTT LDO to
soft start. To ensure that the VDDQ output is not subjected to large transient currents during transition, the VTT and 1.2V
LDO slew rates are limited by the slew rate of the C_SS until the LDO is in regulation. In addition, the VTT regulator is
current limited.
T8 (S0 to S3) : Dropping the S3#I signal. When this occurs, VCC_EN goes low, and the 3.3V LDO turns on. The 1.2V
LDO and the VTT LDO are turned off, and C_SS is discharged to 2V. 5VSB_DRV pulls low to turn on the P-Channel 5V
DUAL switch.
DS9643-03 August 2007
www.richtek.com
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