RT8015A Datasheet, PDF (3/14 Pages) Richtek Technology Corporation – 3A, 2MHz, Synchronous Step-Down Converter

Function Block Diagram
SHDN/RT
SD
COMP
0.8V
EA
FB
OSC
Output
Clamp
Slope
Com
ISEN
OC
Limit
RT8015A
PVDD
Int-SS
POR
0.9V
0.7V
0.4V
Control
Logic
Driver
NISEN
NMOS I Limit
LX
PGND
V_REF OTP
GND
VDD
Layout Guide
C_IN must be placed between V_DD
Output capacitor must be
and GND as closer as possible
near RT8015A
V_IN
GND
C_IN
C_OUT
V_OUT ^{LX should be}
connected to Inductor
by wide and short
trace, keep sensitive
RT8015A
L1 ^{components away}
from this trace
C_F ^R1 R2
PVDD 6
PVDD 7
VDD 8
FB 9
COMP 10
R_COMP
5 PGND
4 LX
3 LX
2 GND
1 SHDN/RT
R_OSC
V_OUT
C_COMP
GND
Connect the FB pin directly to feedback resistors. The
resistor divider must be connected between V_OUT and GND.
DS8015A-04 March 2011
www.richtek.com
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