RT8857 Datasheet, PDF (23/26 Pages) Richtek Technology Corporation – 4/3/2/1-Phase PWM Controller with Embedded Drivers for CPU Core Power Supply

RT8857/A
voltage loop will be the main task to maintain converter
stability.
The converter duty-to-output transfer function G_d is :
V_OUT
G_d =
D
(13)
1+ ^S + ^S2
R ^{L ⎛} 1 ^⎞2
C
⎜
⎝
LC
⎟
⎠
and the modulator gain of the converter is :
F_m
=
1
V_P
(14)
Where V_OUT is the output voltage of the converter, R is
the loading resistance, L and C are the output inductance
and capacitance, and V_P is the peak-to-peak voltage of
ramp applied at modulator input. The overall loop gain after
compensation can be described as :
Loop Gain = T = G_d x F_m x A
(15)
Where A denotes as compensation gain. To compensate
a typical voltage mode buck converter, there are two
ordinary compensation schemes, well known as type-II
compensator and type-III compensator. The choice of using
type-II or type-III compensator will be up to platform
designers, and the main concern will be the position of
the capacitor ESR zero and mid-frequency to high-
frequency gain boost. Typically, the ESR zero of output
capacitor will tend to stabilize the effect of output LC double
poles, hence the positon of the output capacitor ESR zero
in frequency domain may influence the design of voltage
loop compensation. If F_ZERO,ESR is <1/2F_CO where F_CO
denotes cross-over frequency, type-II compensation will
be sufficient for voltage stability. If F_ZERO,ESR is > 1/2F_CO
(or higher gain and phase margin is required at mid-
frequency to high-frequency), then type-III compensation
may be a better solution for voltage loop compensation.
A typical type-II compensation network is shown in
Figure 14.
C2
R2 ^C1
R1
-
EA
+
+
-
V_REF
Figure 14. Type-II Compensation
R1 can be determined independently from DC
considerations. Normally choose R1 that the current
passing by will be around 1mA. Therefore,
R1 = ^VREF
(16)
1mA
Then determine R2 by the boosted gain of loop gain at
crossover :
R2
=
R1×
V_P
V_IN(MAX)
×
⎛
⎜⎝
F_{ZERO, ESR}
F_LC
⎞²
⎟⎠
×
F_CO
F_{ZERO, ESR}
(17)
Where V_IN(MAX) is the max input voltage of power stage,
V_P is the peak-to-peak voltage of ramp applied at modulator
input, F_ZERO,ESR is the frequency of output capacitor ESR
zero, and F_LC is the frequency of output LC :
F_ZERO,
ESR
=
2π
1
× R_ESR
×C
(18)
F_LC =
1
(19)
2π × LC
After determining the phase margin at crossover
frequency, the position of zero and pole produced by
type-II compensation network, F_Z and F_P, can then be
determined. The bode plot of type-II compensation is
shown in Figure15, where
F_Z
F_P
Frequency (Hz)
Figure 15. Bode Plot of Type-II Compensation
DS8857/A-01 April 2011
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