RT7274 Datasheet, PDF (20/22 Pages) Richtek Technology Corporation – 2A, 18V, 700kHz ACOTTM Synchronous Step-Down Converter

RT7274/79/80/81
package, the thermal resistance, θ_JA, is 49°C/W on a
standard JEDEC 51-7 four-layer thermal test board. The
maximum power dissipation at T_A = 25°C can be calculated
by the following formulas :
P_D(MAX) = (125°C − 25°C) / (40°C/W) = 2.50W for
TSSOP-14 (Exposed Pad) package
P_D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on operating
ambient temperature for fixed T_J(MAX) and thermal
resistance, θ_JA. The derating curves in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.0
TSSOP-14 (Exposed Pad)
2.5
Four-Layer PCB
2.0
1.5
SOP-8 (Exposed Pad)
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7274/79/80/81
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` SW node is with high frequency voltage swing and
should be kept at small area. Keep sensitive
components away from the SW node to prevent stray
capacitive noise pickup.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7274/79/80/81 FB pin.
` The GND and Exposed Pad should be connected to a
strong ground plane for heat sinking and noise protection.
Place the feedback components
as close to the FB as possible
for better regulation.
V_OUT
R1
VOUT
PGND
14
FB
2
13
R2 _CVCC
PVCC
SS
3
12
4 _PGND 11
GND
5
10
PGOOD
6
EN
7
15 ⁹
8
Place the input and output
capacitors as close to the
IC as possible.
VINR
VIN
BOOT
SW
SW
PGND
PGND
C_IN
C_BOOT
L _VOUT
C_OUT
SW should be connected to inductor by
Wide and short trace. Keep sensitive
components away from this trace.
(a). For TSSOP-14 (Exposed Pad) Package
The resistor divider must
be connected as close to
the device as possible.
V_OUT
GND
R1
R2
C4
C5
EN
FB
PVCC
SS
Input capacitor must be placed
C1 ^{as close to the IC as possible.}
C2
SW should be connected to inductor by
Wide and short trace. Keep sensitive
8
VIN _{components away from this trace.}
2
7
BOOT
GND
C6
3
6
SW
9
4
5
GND
L1
C7
(b). For SOP-8 (Exposed) Package
Figure 7. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
DS7274/79/80/81-01 February 2013