RT2702 Datasheet, PDF (18/20 Pages) Richtek Technology Corporation – Step-Down DC-DC Controller

RT2702
Organic semiconductor capacitor(s) or specialty polymer
capacitor(s) are recommended.
The amount of overshoot due to stored inductor energy
can be calculated as :
V_SOAR

(I_PEAK )²  L
2  C_OUT  V_OUT
where I_PEAK is the peak inductor current.
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T_J(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
P_D(MAX) = (T_J(MAX) − T_A) / θ_JA
where T_J(MAX) is the maximum junction temperature, T_A is
the ambient temperature, and θ_JA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θ_JA, is highly package dependent. For a
WQFN-16L 3x3 package, the thermal resistance, θ_JA, is
30°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at T_A = 25°C can be calculated as below :
P_D(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for a
WQFN-16L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for the fixed T_J(MAX) and the thermal
resistance, θ_JA. The derating curves in Figure 9 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
18
4.0
Four-Layer PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 9. Derating Curve of Maximum Power Dissipation
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to converter
instability. Certain points must be considered before
starting a layout for the RT2702.
 Connecting capacitors to VIN and VDRV are
recommended. Place these capacitors close to the IC.
 Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.
 Connections from the RT2702 to DrMOS should be as
short as possible to reduce stray inductance.
 All sensitive analog traces and components such as
TON, EN, ILIM, SS, FB, CSN, CSP, POK, MODE,
PWM, DISB , THWN , GND and RGND should be
placed away from high voltage switching nodes such as
PHASE nodes to avoid coupling. Use internal layer(s)
as ground plane(s) and shield the feedback trace from
power traces and components.
 Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
 Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
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DS2702-00 October 2016