RT8100 Datasheet, PDF (16/18 Pages) Richtek Technology Corporation – Synchronous buck PWM DC/DC with Dual Voltage Control Mode

RT8100
Preliminary
where T_DIODE is the conducting time of lower body diode.
Special control scheme is adopted to minimize body diode
conducting time. As a result, the R_DS(ON) loss dominates
the power loss of lower MOSFET. Use MOSFET with
adequate R_DS(ON) to minimize power loss and satisfy
thermal requirements.
Bypass Capacitor Notes
Input capacitor C_IN is typically chosen based on the ripple
current requirements. C_OUT is typically selected based on
both current ripple rating and ESR requirement.
PWM Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability.
First, place the PWM power stage components. Mount all
the power components and connections in the top layer
with wide copper areas. The MOSFETs of Buck, inductor,
and output capacitor should be as close to each other as
possible. This can reduce the radiation of EMI due to the
high frequency current loop. If the output capacitors are
placed in parallel to reduce the ESR of capacitor, equal
sharing ripple current should be considered. Place the input
capacitor directly to the drain of high-side MOSFET. In
multi-layer PCB, use one layer as power ground and have
a separate control signal ground as the reference of the all
signal. To avoid the signal ground is effect by noise and
have best load regulation, it should be connected to the
ground terminal of output. Furthermore, follows below
guidelines can get better performance of IC :
1. A multi-layer printed circuit board is recommended.
2. Use a middle layer of the PC board as a ground plane
and making all critical component ground connections
through vias to this layer.
3. Use another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
4. Keep the metal running from the PHASE terminal to
the output inductor short.
5. Use copper filled polygons on the top and bottom circuit
layers for the phase node.
6. The small signal wiring traces from the LGATE and
UGATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the several Amperes
of drive current.
7. The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position those components close to their
pins with a local GND connection, or via directly to the
ground plane.
8. R_T resistors should be near the R_T pin respectively, and
GND return should be short, and kept away from the
noisy MOSFET GND.
9. Place the compensation components close to the FB
and COMP pins.
10. The feedback resistors should also be located as close
as possible to the relevant FB pin with vias tied straight
to the ground plane as required.
11. Minimize the length of the connections between the
input capacitors, C_IN and the power switches by placing
them nearby.
12. Position both the ceramic and bulk input capacitors as
close to the upper MOSFET drain as possible, and make
the GND returns (From the source of lower MOSFET to
V_IN, C_VIN, GND) short.
13. Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET and
the load.
14. Because RT8100 use DCR sense topology, DCR sense
point is output inductor from end to end.
15. CSN and FB must be independent path.
Below PCB gerber files are our test board for your
reference :
www.richtek.com
16
DS8100-03 August 2007