RT9210 Datasheet, PDF (14/17 Pages) Richtek Technology Corporation – Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination

RT9210
Preliminary
Feedback Compensation
The RT9210 is a voltage mode controller; the control loop
is a single voltage feedback path including an error amplifier
and PWM comparator as Figure 1 shows. In order to
achieve fast transient response and accurate output
regulation, a adequate compensator design is necessary.
The goal of the compensation network is to provide
adequate phase margin (greater than 45 degrees) and the
highest 0dB crossing frequency. And to manipulate loop
frequency response that its gain crosses over 0dB at a
slope of -20dB/dec.
Vin
PWM
PWM
+
Comparator
-
VRAMP
Lo
Vout
Co
ESR
Zf
-
+
Zc
VREF
Compensator
Figure 1
Modulator Frequency Equations
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This transfer function is dominated
by a DC gain and the output filter (L_O and C_O), with a
double pole
frequency at F_LC and a zero at F_ESR. The DC gain of the
modulator is the input voltage (V_IN) divided by the peak-
to-peak oscillator voltage V_RAMP.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
The output LC filter introduces a double pole,−40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 degrees. The Resonant
frequency of the LC filter expressed as follows :
1
FP(LC) =
2π × LO × CO
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
1
FZ(ESR) =
2π × CO × ESR
Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z_C and Z_F as Figure 2 shows.
Zf
C1
Zc
R1
R2
C2
-
EA
COMP1
+
FB1
Rf
RT9210
VREF
VOUT
FP1 = 0
Figure 2
1
FZ1 =
2π × R2 × C2
1
FP1 =
2π × R2 (C1// C2)
Figure 3 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
Z_C and Z_F to provide a stable, high bandwidth loop.
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DS9210-05 March 2007