RT7259 Datasheet, PDF (14/15 Pages) Richtek Technology Corporation – 10A, 24V, 600kHz Step-Down Converter with Synchronous Gate Driver

RT7259
The maximum power dissipation at T_A = 25°C can be
calculated by the following formulas :
P_D(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-14L 4x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T_J(MAX) and thermal
resistance, θ_JA. For the RT7259 package, the derating
curves in Figure 8 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
1.80
Four-Layer PCB
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curves for RT7259 Package
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7259.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick-up.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7259.
` Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
` An example of PCB layout guide is shown in Figure 9
for reference.
GND
R2
V_OUT
R3
V_CC
R1
FB 1
PGOOD 2
GND EN/SYNC 3
The EN/SYNC must be kept
away from noise. The trace
should be short and shielded
with a ground trace.
V_IN
C_IN
VIN ⁴
VIN 5
VIN 6
NC 7
The feedback components
must be connected as close
to the device as possible.
14 _GND
C_VCC capacitor must
be placed as close to
the IC as possible.
13 BG
12 VCC
C_VCC
GND
15
11 BOOT
10 SW
9 SW
8 SW
Q1
C_BOOT
L ^VOUT
BG
C_OUT
SW should be connected
to inductor by wide and
short trace. Keep sensitive
components away from
this trace.
Input capacitor must be
placed as close to the
IC as possible.
GND
Figure 9. PCB Layout Guide
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS7259-00 January 2012