RT6255A Datasheet, PDF (14/20 Pages) Richtek Technology Corporation – ACOT Step-Down Converter

RT6255A/B
Output Ripple Voltage
Output ripple voltage at the switching frequency is caused
by the inductor current ripple and its effect on the output
capacitor's ESR and stored charge. These two ripple
components are called ESR ripple and capacitive ripple.
Since ceramic capacitors have extremely low ESR and
relatively little capacitance, both components are similar
in amplitude and both should be considered if ripple is
critical.
V_RIPPLE = V_RIPPLE(ESR)  V_RIPPLE(C)
V_RIPPLE(ESR) = I_L R_ESR
V_RIPPLE(C)
=
I_L
8  C_OUT  f_SW
The typical operating circuit design for the RT6255A/B,
the output voltage is 1V, inductor ripple current is 1.23A,
and using 2 pieces of 22μF output capacitor with about
5mΩ ESR, the output voltage ripple components are :
V_RIPPLE(ESR) = I_L R_ESR = 1.23A  5m = 6.15mV
V_RIPPLE(C)
=
I_L
8  C_OUT  f_SW
=
1.23A
8  44μF 500kHz
= 6.99mV
V_RIPPLE = V_RIPPLE(ESR)  V_RIPPLE(C) = 13.13mV
Output Transient Undershoot and Overshoot
In addition to output ripple voltage at the switching
frequency, the output capacitor and its ESR also affect
the voltage sag (undershoot) and soar (overshoot) when
the load steps up and down abruptly. The ACOT^TM transient
response is very quick and output transients are usually
small. However, the combination of small ceramic output
capacitors (with little capacitance), low output voltages
(with little stored charge in the output capacitors), and
low duty cycle applications (which require high inductance
to get reasonable ripple currents with high input voltages)
increases the size of voltage variations in response to
very quick load changes. Typically, load changes occur
slowly with respect to the IC's 500kHz switching frequency.
But some modern digital loads can exhibit nearly
instantaneous load changes and the following section
shows how to calculate the worst-case voltage swings in
response to very fast load steps.
The output voltage transient undershoot and overshoot each
have two components : the voltage steps caused by the
output capacitor's ESR, and the voltage sag and soar due
to the finite output capacitance and the inductor current
slew rate. Use the following formulas to check if the ESR
is low enough (typically not a problem with ceramic
capacitors) and the output capacitance is large enough to
prevent excessive sag and soar on very fast load step
edges, with the chosen inductor value.
The amplitude of the ESR step up or down is a function of
the load step and the ESR of the output capacitor :
V_{ESR_STEP} = I_OUT R_ESR
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle. The maximum duty cycle during a fast transient
is a function of the on-time and the minimum off-time since
the ACOT^TM control scheme will ramp the current using
on-times spaced apart with minimum off-times, which is
as fast as allowed. Calculate the approximate on-time
(neglecting parasitics) and maximum duty cycle for a given
input and output voltage as :
t _ON
=
V_OUT
V_IN  f_SW
and D_MAX
=
t_ON
t_ON  t_{OFF_MIN}
The actual on-time will be slightly longer as the IC
compensates for voltage drops in the circuit, but we can
neglect both of these since the on-time increase
compensates for the voltage losses. Calculate the output
voltage sag as :
  ^VSAG
=
2 C_OUT 
L  (I_OUT )²
V_IN(MIN) D_MAX  V_OUT
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor value
and the output voltage :
V_SOAR
=
L  (I_OUT )²
2  C_OUT  V_OUT
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DS6255A/B-02 March 2017