RT9275 Datasheet, PDF (13/14 Pages) Richtek Technology Corporation – Tiny Package, High Efficiency, Step-Up DC/DC Converter

Preliminary
RT9275
Application Information
Output Voltage Setting
Referring to Typical Application Circuits, the output voltage
of the switching regulator (V_OUT) can be set with Equation
(1).
R1
VOUT = ( 1+ ) ×1.25V
(1)
R2
Feedback Loop Design
Referring to Typical Application Circuits. The selection of
R1 and R2 based on the trade-off between quiescent current
consumption and interference immunity is stated below:
z Follow Equation (1)
z Higher R reduces the quiescent current (Path current =
1.25V/R2), however resistors beyond 5MΩ are not
recommended.
z Lower R gives better noise immunity, and is less sensitive
to interference, layout parasitics, FB node leakage, and
improper probing to FB pins.
V_OUT
Layout Guide
z A full GND plane without gap break.
z V_DD to GND noise bypass − Short and wide connection
for the 1μF MLCC capacitor between Pin5 and Pin3.
z V_IN to GND noise bypass − Add a capacitor close to L1
inductor, when V_IN is not an idea voltage source.
z Minimized FB node copper area and keep far away from
noise sources.
z Minimized parasitic capacitance connecting to LX and
EXT nodes, which may cause additional switching loss.
Board Layout Example (2-Layer Board)
(Refer to Typical Application Circuit for the board)
Prober Parasitics
_
Q
+
R1
FB Pin
R2
z A proper value of feed forward capacitor parallel with R1
can improve the noise immunity of the feedback loops,
especially in an improper layout. An empirical suggestion
is
1 _{= 10 to 20kHz}
2πR1C4
For applications without standby or suspend modes, lower
values of R1 and R2 are preferred. For applications
concerning the current consumption in standby or suspend
modes, the higher values of R1 and R2 are needed. Such
“high impedance feedback loops” are sensitive to any
interference, which require careful layout and avoid any
interference, e.g. probing to FB pin.
- Top Layer -
DS9275-06 March 2007
- Bottom Layer -
www.richtek.com
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