RT8886A Datasheet, PDF (13/45 Pages) Richtek Technology Corporation – 2-Phase Controller with Dual Integrated Drivers

RT8886A
Index
00h
01h
02h
05h
06h
10h
11h
12h
15h
1Ch
21h
22h
24h
25h
2Ah
2Bh
2Ch
2Dh
30h
31h
32h
33h
34h
35h
Register Name
Vendor ID
Product ID
Product Revision
Protocol ID
Capability
Status_1
Status_2
Temperature
Zone
IOUT
Status_2_lastread
ICC Max
Temp Max
SR-fast
SR-slow
Slow Slew Rate
Selector
PS4 Exit Latency
PS3 Exit Latency
Enable to Ready
for SVID
VOUT Max
VID Setting
Power State
Offset
Multi VR
Configuration
Pointer
Table3. SVID Data and Configuration Register
Description
Access
Vendor ID
RO, Vendor
Product ID
RO, Vendor
Product Revision
RO, Vendor
SVID Protocol ID
RO, Vendor
Bit mapped register, identifies the SVID VR Capabilities
and which of the optional telemetry register is supported.
RO, Vendor
Data register containing the status of VR.
R-M, W-PWM
Data register containing the status of transmission.
R-M, W-PWM
Data register showing temperature zone that has been
entered.
R-M, W-PWM
At PS0 to PS2, IOUT report data from ADC sense IMON
voltage. When power state at PS3, the IOUT report data R-M, W-PWM
is fix to 04h.
The register contains a copy of the status_2.
R-M, W-PWM
Data register containing the ICC max the platform
supports. Binary format in A IE 64h = 100A.
RO, Platform
Data register containing the temperature max the
platform supports.
RO, Platform
Binary format in C IE 64h = 100C.
Data register containing the capability of fast slew rate the
platform can sustain. Binary format in mV/S IE 0Ch =
RO
12mV/s.
Data register containing the capability of slow slew rate.
Binary format in mV/S IE 03h = 3mV/S.
RO
The register is programmed by master and set the slow
slew rate.
RW, Master
Data register containing the latency of exiting PS4.
RO
Data register containing the latency of exiting PS3.
RO
Data register containing the latency from Enable
assertion to the VR being ready to accept an SVID
RO
command.
The register is programmed by master and sets the
maximum VID.
RW, Master
Data register containing currently programmed VID.
RW, Master
Register containing the current programmed power state. RW, Master
Set offset in VID steps.
RW, Master
Bit mapped data register which configures multiple VRs
behavior on the same bus.
RW, Master
Scratch pad register for temporary storage of the
SetRegADR pointer register.
RW, Master
Default
1Eh
84h
00h
02h
81h
00h
00h
00h
00h
00h
7Dh
64h
0Ch
03h
02h
7Fh
3Fh
BFh
D5h
00h
00h
00h
00h
30h
Notes :
RO = Read Only
RW = Read/Write
R-M = Read by Master
W-PWM = Write by PWM Only
Vendor = Hard Coded by VR Vendor
Platform = Programmed by the Master
PWM = Programmed by the VR Control IC
Copyright ©2013 Richtek Technology Corporation. All rights reserved.
DS8886A-00 November 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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