RT8100A Datasheet, PDF (13/18 Pages) Richtek Technology Corporation – Synchronous buck PWM DC/DC with Dual Voltage Control Mode

Preliminary
RT8100A
Feedback Loop Compensation
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the RR pin.
This keeps the modulator gain constant when the input
voltage varies. Second, the inductance valley current
proportional signal is derived from the voltage drop across
the ESR of the inductance is added to the ramp signal.
This effectively creates an internal current control loop.
The resistor connected to the CSN pin sets the gain in the
current feedback loop. The following expression estimates
the required value of the current sense resistor depending
on the maximum load current and the value of the
inductance DCR.
R_CSN
= I_MAX
x
DCR
80μA
1) Modulator Frequency Equations
RT8100A is a analogous current mode buck converter
using the high gain error amplifier with transconductance
(OTA, Operational Transconductance Amplifier), as Figure
6 shown.
The Transconductance :
GM =
ΔIOUT
ΔVM
Δ V_M = (EA+) - (EA-) ; Δ I_OUT = E/A output current.
EA+ ⁺
EA- _-
GM
V_OUT
R_OUT
Figure 6. OTA Topology
This transfer function of OTA is dominated by a higher DC
gain and the output filter (L_OUT and C_OUT) with a double
pole frequency at F_LC and a zero at F_ESR. The DC gain of
the modulator is the input voltage (V_IN) divided by the peak
to peak oscillator voltage V_RAMP.
DS8100A-01 August 2007
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter expressed as follows :
FP(LC) =
1
2π × LOUT × COUT
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
FZ(ESR)
=
2π
1
× COUT
× ESR
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z_C and Z_F as Figure 7 shown.
V_OUT
FB
R1 ^VREF
+
GM
-
C2
V_COMP
C1
R2
R_F
Figure 7. Compensation Loop
FZ1
=
2π
1
×R2× C2
FP1
=
2π
1
×R1× C1
FP2
=
2π
1
×
R2
×
⎜⎝⎛
C1×
C1+
C2
C2
⎟⎠⎞
Figure 8 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop. High
crossover frequency is desirable for fast transient response,
but often jeopardize the system stability. In order to cancel
one of the LC filter poles, place F_Z1 before the LC filter
resonant frequency. In the experience, place F_Z1 at 10%
LC filter resonant frequency. Crossover frequency should
be higher than the ESR zero but less than 1/5 of the
switching frequency. The F_P2 should be place at half the
switching frequency.
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