RT7263A Datasheet, PDF (12/17 Pages) Richtek Technology Corporation – 3A, 21V 500kHz Synchronous Step-Down Converter

RT7263A
EN
R_EN
V_IN
C_EN
EN
RT7263A
GND
Figure 3. Enable Timing Control
An external MOSFET can be added to implement digital
control on the EN pin, as shown in Figure 4. In this case,
a 100kΩ pull-up resistor, R_EN, is connected between V_IN
pin and the EN pin. MOSFET Q1 will be under logic control
to pull down the EN pin.
R_EN
100k
V_IN
EN
EN
Q1 ^RT7263A
GND
Figure 4. Digital Enable Control Circuit
The chip starts to operate when V_IN rises to 4.2V (UVLO
threshold). During the V_IN rising period, if an 8V output
voltage is set, V_IN is lower than the V_OUT target value and
it may cause the chip to shut down. To prevent this
situation, a resistive voltage divider can be placed between
the input voltage and ground and connected to the EN pin
to adjust enable threshold, as shown in Figure 5. For
example, the setting V_OUT is 8V and V_IN is from 0V to
12V, when V_IN is higher than 10V, the chip is triggered to
enable the converter. Assume R_EN1 = 50kΩ. Then,
R_EN2
=
(R_EN1
(V_{IN_S}
x
−
V_IH(MIN) )
V_IH(MIN) )
where V_IH(MIN) is the minimum threshold of enable rising
(2V) and V_{IN_S} is the target turn on input voltage (10V in
this example). According to the equation, the suggested
resistor R _EN2 is 12.5kΩ.
R_EN1
V_IN
R_EN2
EN
RT7263A
GND
Figure 5. Resistor Divider for Lockout Threshold Setting
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
Operating Frequency and Synchronization
The internal oscillator runs at 500kHz (typ.) when the EN/
SYNC pin is at logic-high level (>2V). If the EN pin is
pulled to low-level for 10μs above, the IC will shut down.
The RT7263A can be synchronized with an external clock
ranging from 300kHz to 2MHz applied to the EN/SYNC
pin. The external clock duty cycle must be from 30% to
90%.
2ms
10µs
VIN
EN/SYNC
VCC
VOUT
CLK
External CLK
Figure 6. Startup Sequence Using External Sync Clock
Figure 6 shows the synchronization operation in startup
period. When the EN/SYNC is triggered by an external
clock, the RT7263A enters soft-start phase and the output
voltage starts to rise. During the soft-start phase region,
the oscillation frequency will be proportional to the feedback
voltage until it is higher than 0.7V. With higher V_FB, the
switching frequency is relatively higher. After startup period
about 2ms, the IC operates with the same frequency as
the external clock.
Power Good Output
The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is lower than
70% of its set voltage, PGOOD will be pulled low. It is
held low until the output voltage returns to within the allowed
tolerances once more. During soft-start, PGOOD is actively
held low and only allowed to transition high after soft-start
is over and the output voltage has reached 90% of its set
voltage.
Output Under Voltage Protection (Hiccup Mode)
For the IC, Hiccup Mode of Under Voltage Protection (UVP)
is provided. When the FB voltage drops below half of the
feedback reference voltage, V_FB, the UVP function will be
triggered and the IC will shut down for a period of time and
then recover automatically. The Hiccup Mode of UVP can
reduce input current in short-circuit conditions.
is a registered trademark of Richtek Technology Corporation.
DS7263A-01 September 2012