RT7247B Datasheet, PDF (12/15 Pages) Richtek Technology Corporation – 2A, 18V, 1.2MHz Synchronous Step-Down Converter

RT7247B
C_IN and C_OUT Selection
The input capacitance, C_IN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
approximate RMS current is given :
I_RMS
=
I_OUT(MAX)
V_OUT
V_IN
V_{IN −1}
V_OUT
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT/2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required. Several
capacitors may also be paralleled to meet size or height
requirements in the design. For the input capacitor, two
10μF low ESR ceramic capacitors are suggested. For the
suggested capacitor, please refer to Table 3 for more
details. The selection of C_OUT is determined by the
required ESR to minimize voltage ripple. Moreover, the
amount of bulk capacitance is also a key for _COUT selection
to ensure that the control loop is stable. Loop stability
can be checked by viewing the load transient response
as described in a later section.
The output ripple, ΔV_OUT , is determined by :
ΔV_OUT
≤
ΔI_L
⎡⎢⎣_{ESR +}
1
8fC_OUT
⎤
⎥⎦
The output ripple will be the highest at the maximum input
voltage since ΔI_L increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, V_IN. A sudden inrush
of current through the long wires can potentially cause a
voltage spike at V_IN large enough to damage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P_D(MAX) = (T_J(MAX) − T_A ) / θ_JA
Where T_J(MAX) is the maximum operation junction
temperature , T_A is the ambient temperature and the θ_JA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT7247B, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θ_JA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θ_JA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at T_A = 25°C can be calculated by following
formula :
P_D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P_D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm²copper area PCB layout)
The thermal resistance θ_JA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to increase
thermal performance by the PCB layout copper design.
The thermal resistance θ_JA can be decreased by adding
copper area under the exposed pad of SOP-8 (Exposed
Pad) package.
As shown in Figure 7, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 7.a), θ_JA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 7.b) reduces the θ_JA to 64°C/W. Even further,
increasing the copper area of pad to 70mm² (Figure 7.e)
reduces the θ_JA to 49°C/W.
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS7247B-01 September 2012