RT7237A Datasheet, PDF (12/15 Pages) Richtek Technology Corporation – 2A, 18V, 340kHz Synchronous Step-Down Converter

RT7237A
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
L
=
⎡
⎢⎣
f
×
V_OUT
ΔI_L(MAX)
⎤
⎥⎦
×
⎡⎢⎣_1−
V_OUT
V_IN(MAX)
⎤
⎥⎦
The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
Table 2. Suggested Inductors for Typical
Application Circuit
Component
Supplier
TDK
Series
VLF10045
Dimensions
(mm)
10 x 9.7 x 4.5
TDK
SLF12565 12.5 x 12.5 x 6.5
T AIYO
YUDEN
NR8040
8x8x4
C_IN and C_OUT Selection
The input capacitance, C_IN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
approximate RMS current equation is given :
I_RMS
=
I_OUT(MAX)
V_OUT
V_IN
V_{IN −1}
V_OUT
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT / 2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input capacitor, two 10μF low ESR ceramic
capacitors are suggested. For the suggested capacitor,
please refer to Table 3 for more details.
The selection of C_OUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for C_OUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response as described in a later section.
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
The output ripple, ΔV_OUT , is determined by :
ΔV_OUT
≤
ΔI_L
⎡⎢⎣_ESR
+
1
8fC_OUT
⎤
⎥⎦
The output ripple will be the highest at the maximum input
voltage since ΔI_L increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, V_IN. At worst, a
sudden inrush of current through the long wires can
potentially cause a voltage spike at V_IN large enough to
damage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P_D(MAX) = (T_J(MAX) − T_A ) / θ_JA
Where T_J(MAX) is the maximum operation junction
temperature , T_A is the ambient temperature and the θ_JA is
the junction to ambient thermal resistance.
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θ_JA is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance
θ_JA is 75°C/W on the standard JEDEC 51-7 four-layers
thermal test board. The maximum power dissipation at
T_A = 25°C can be calculated by following formula :
P_D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P_D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm²copper area PCB layout)
is a registered trademark of Richtek Technology Corporation.
DS7237A-01 September 2012