RT9202B Datasheet, PDF (11/14 Pages) Richtek Technology Corporation – Single Synchronous Buck PWM DC-DC Controller

RT9202B
Table 1
V_OUT
Inductor
3.3V
2µH
5µH
2.5V
2µH
5µH
1000µF (ESR=53mΩ) 100mV 40mV 110mV 44mV
1500µF (ESR=33mΩ) 62mV 25mV 68mV 28mV
3000µF (ESR=21mΩ) 40mV 16mV 43mV 18mV
*Refer to Sanyo low ESR series (CE, DX, PX.....)
1.5V
2µH
5µH
93mV 37mV
58mV 23mV
37mV 15mV
The suggested L and C are as follows:
2µH with ≥ 1500µF C_OUT
5µH with ≥ 1000µF C_OUT
L
Q
V_L
V_I
D
C
R V_O
C.C.M
T_S
T_ON
T_OFF
V_I - V_O
Input / Output Capacitor
High frequency/long life decoupling capacitors should be
placed as close to the power pins of the load as physically
possible. Be careful not to add inductance to the PCB
trace, as it could eliminate the performance from utilizing
these low inductance components. Consult with the
manuf acturer of the load on specific decoupling
requirements.
The output capacitors are necessary for filtering output
and stabilizing the close loop (see the PWM loop stability).
For powering advanced, high-speed processors, it is
required to meet with the requirement of fast load
transient, high frequency capacitors with low ESR/ESL
capacitors are recommended.
V_L
- V_O
Another concern is high ESR induced ripple may trigger
UV or OV protections.
PWM Loop Stability
i_L
uQ
I_L = I_O
The RT9202B is a voltage mode buck controller designed
mI_L
for 5V step-down applications. The gain of error amplifier
is fixed at 35dB for simplified design.
The output amplitude of ramp oscillator is 1.75V, the loop
gain and loop pole/zero are calculated as follows :
i_Q
I_Q
DC loop gain G_A =
35dB
×
5
1.75
×
0.8
V_OUT
LC filter pole P_O = ¹
2π LC
i_D
Error Amp pole P_A = 300kHz
I_D
ESR zero Z_O =
2π
1
ESRC
The RT9202B Bode plot as shown Figure 6 is stable in
Figure 5
most of application conditions.
DS9202B-03 March 2007
www.richtek.com
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