RT9108N Datasheet, PDF (11/14 Pages) Richtek Technology Corporation – 15W Stereo Class-D Audio Power Amplifier

Application Information
Amplifier Gain Setting
The gain of the RT9108N amplifier can be set by two input
terminals, GAIN0 and GAIN1, shown as Table 1.
The gain setting is realized by changing the taps on the
input resistors and feedback resistors inside the amplifier.
This causes the input impedance (Z_I) to be dependent on
the gain setting. The actual gain settings are controlled
by the ratios of the resistors, so the gain variation from
part-to-part is small. However, the input impedance from
part-to-part at the same gain may shift by ±20% due to
shifts in the actual resistance of the input resistors.
GAIN1
0
Table 1. Gain Setting
GAIN0
Amplifier
GAIN (dB)
Typ
Input Impedance
(kΩ)
Typ
0
20
100
0
1
26
50
1
0
32
25
1
1
36
12.5
SD Operation
The RT9108N employs a shutdown mode operation
designed to reduce supply current (I_CC) to the absolute
minimum level for power saving. The SD input terminal
should be held high (see specification table for trip point)
in normal operation. Pulling SD low causes the outputs
to mute and the amplifier to enter a low current state.
Leaving SD floating will cause the amplifier operation to
be unpredictable. Never leave SD pin unconnected!
RT9108N
For the best power-off pop performance, turn off the
amplifier in the shutdown mode prior to removing the power
supply voltage.
GVDD Supply
The GVDD is used to supply the Gate Drivers for the output
full bridge transistors. Connect a 1μF capacitor from this
pin to ground for good bypass. The typical GVDD output
voltage is 4.6V.
Power Limit
The output power limit is programmable by the PLIMIT
pin voltage level. Table 2 and Table 3 show the Width-
Factor and maximum output power with different PLIMIT
voltages. The voltage setting at PLIMIT pin can be achieved
by using a resistive divider between GVDD pin and AGND
pin or using an external reference voltage. It's
recommended to add a 1μF capacitor from the PLIMIT to
AGND for noise reduction. The output power can be
estimated by the following equation.
Output Power = ^PVCC2 ×(Width_Factor)
R_L ×1.35
Table 2. PLIMIT Voltage and Width-Factor
PLIMIT Voltage (V)
4.6 (GVDD)
2.8 to 2.9
2.4 to 2.5
2.1 to 2.2
1.6 to 1.7
1.3 to 1.4
Width_Factor
1
0.765
0.578
0.41
0.265
0.149
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS9108N-00 June 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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