RT8805 Datasheet, PDF (11/15 Pages) Richtek Technology Corporation – Two Phase General Purpose PWM Controller

Preliminary
RT8805
80 ⁸⁰
Loop Gain
60
40 ⁴⁰
20
Compensation
Gain
0⁰
Modulator
-20 _Gain
-40^-40
-60-60
1^10H0^zvdb(vo) _vdb(comp2)1¹⁰0^0vHd0^zb(lo)
1^1.0k^KHz
1₁0K₀Hz_k
Frequ^Fre^equn^encc^yy (Hz)
1¹⁰0^0K0^Hzk
1.0₁MH_Mz
Figure 8. Type 2 Bode Plot
There is another type of compensation called Type 3
compensation that adds a pole-zero pair to the Type 2
network. It's used to compensate output capacitor whose
ESR value is much lower (pure MLCC or OSCON
Capacitors).
As shown in Figure 9, to insert a network between V_OUT
and FB in the original Type 2 compensation network can
result in Type 3 compensation. Figure 10 shows the
difference of their AC response. Type 3 compensation has
an additional pole-zero pair that causes a gain boost at
the flat gain region. But the gain boosted is limited by the
ratio (R1+R4)/R4; if R3 << R4.
V_OUT
C3 _R3
R1
+
FB GM
-
C2
V_COMP
C1
R4
R2
Figure 9. Additional Network of Type 3 Compensation
(Add between V_OUT and FB)
F_P3
Add Type 3 compensation
F_P1
Pole
F_P2
F_Z1
F_Z2
Original Type 3 compensation
Figure 10. AC Response Curves of Type 2 and 3
DS8805-01 November 2005
Type 3 will induce three poles and two zeros.
Zeros :
FZ1
=
2π
1
×R2× C2
FZ2
=
2π
1
× (R1+ R3)× C3
Poles :
FP1
=
2π
1
×
R2
×
⎜⎝⎛
C1×
C1+
C2
C2
⎟⎠⎞
FP2
=
2π
1
×R3 × C3
FP3
=
2π
1
× ⎜⎝⎛ ^R1R×_1R+^3R×_3C1⎟⎠⎞
;
which is in the origin.
We recommend F_Z1 placed in 0.5 x F_P(LC); F_Z2 placed in
F_P(LC); F_P1 placed in F_ESR and F_P2 placed in 0.5 x F_SW.
Figure 11 shows Type 3 Bode Plot.
60
40
20
0
-20
-40
-60
-80
2
Loop Gain
Compensation Gain
Gain
Modulator Gain
3
4
5
6
7
Log Frequency
Figure 11. Type 3 Bode Plot
Protection
OCP
The RT8805 uses “ Cycle by Cycle” current comparison.
The over current level is set by IMAX pin. When OC
function occurs and SS > 3.7V, a constant current of 10μA
starts to discharge the capacitor connected to SS pin
right away. When OC occurs, UGATE and LGATE will be
off.
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