RT8064 Datasheet, PDF (11/13 Pages) Richtek Technology Corporation – 2A, 2MHz, Synchronous Step-Down Converter

RT8064
maximum power dissipation can be calculated by the
following formula :
P_D(MAX) = (T_J(MAX) − T_A) / θ_JA
where T_J(MAX) is the maximum junction temperature, T_A is
the ambient temperature, and θ_JA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ_JA, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θ_JA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-8L 3x3 packages, the
thermal resistance, θ_JA, is 70°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at T_A = 25°C can be calculated by the following
formulas :
P_D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
P_D(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-8L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T_J(MAX) and thermal
resistance, θ_JA. The derating curves in Figure 3 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
Four-Layer PCB
WDFN-8L 3x3
SOP-8 (Exposed Pad)
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the IC.
` Connect the terminal of the input capacitor (s), C<sub>IN</sub>, as
close to the VIN pin as possible. This capacitor provides
the AC current into the internal power MOSFETs.
` LX node experiences high frequency voltage swings so
should be kept within a small area.
` Keep all sensitive small signal nodes away from the LX
node to prevent stray capacitive noise pick up.
` Connect the FB pin directly to the feedback resistors.
The resistive voltage divider must be connected between
V_OUT and GND.
Place the compensation
components as close to
the IC as possible
Place the feedback
resistors as close to
the IC as possible
GND
C_COMP
C_SS
COMP
R_COMP
SS
EN
VIN
GND
C_IN
8
2
7
GND
3
96
4
5
PGOOD
FB
RT
LX
C_OUT
L1
V_IN
V_OUT
Place the input and output capacitors
as close to the IC as possible
R2
R1 _VOUT
R_OSC ^GND
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Place the compensation
components as close to
the IC as possible
Place the feedback
resistors as close to
the IC as possible
GND
C_COMP
R_COMP
C_SS
COMP 1
SS 2
EN 3
VIN ⁴
GND
C_IN
8 PGOOD
7 FB
6 RT
9 5 LX
C_OUT
L1
V_IN
V_OUT
Place the input and output capacitors
as close to the IC as possible
R2
R1 _VOUT
R_OSC ^GND
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace
Figure 4. PCB Layout Guide
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS8064-07 November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11