PLDM4-0.5 Datasheet, PDF (1/1 Pages) Rhombus Industries Inc. – 3-Bit Programmable Delay Modules

3-Bit Programmable Delay Modules
PLDM4 Series FAST/TTL Logic
FAST/TTL 3-Bit Schematic
Vcc
P1 P2 P3
16
11 10 9
7 Delay Steps -- 4 ns Inherent Delay
3-Bit Programmable
Delay Line
Output
Buffer
Available in Surface Mount
Electrical Specifications at 25^OC
4
5
IN OUT
7
8
E GND
3-Bit FAST
Part Number
PLDM4-0.5
PLDM4-0.7
PLDM4-0.8
PLDM4-1
PLDM4-1.2
PLDM4-1.25
PLDM4-1.3
PLDM4-1.5
PLDM4-1.8
PLDM4-2
PLDM4-2.5
PLDM4-2.6
PLDM4-3
Delay per
Step (ns)
0.5 ± .25
0.7 ± .30
0.8 ± .30
1.0 ± .4
1.2 ± .4
1.25 ± .5
1.3 ± .5
1.5 ± .5
1.8 ± .6
2.0 ± .7
2.5 ± .7
2.6 ± .7
3.0 ± .7
Error ref.
to 000
(ns)
± .30
± .40
± .50
± .50
± .60
± .70
± .70
± .70
± .80
± .80
± .90
± .90
± 1.0
Initial
Delay (ns)
000
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
4 ± 1.0
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
000
001
010
011
100
101
110
111
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.7
1.4
2.1
2.8
3.5
4.2
4.9
0.0
0.8
1.6
2.4
3.2
4.0
4.8
5.6
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
0.0
1.2
2.4
3.6
4.8
6.0
7.2
8.4
0.0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
0.0
1.3
2.6
3.9
5.2
6.5
7.8
9.1
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
0.0
1.8
3.6
5.4
7.2
9.0
10.8
12.6
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
0.0
2.6
5.2
7.8
10.4
13.0
15.6
18.2
0.0
3.0
6.0
9.0
12.0
15.0
18.0
21.0
CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000."
For example, the setting "111" delay of PLDM4-10 is 70.0 ± 3.0ns ref. to "_{_}000," and 74.0 ± 4.0ns referenced to the input.
ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.
INPUT FAN-IN: Input, pin 4, is loaded by the internal passive
network and 8 gate inputs (74F type). The source driving Pin 4
should be FAST/TTL (74S/74F) type or equivalent, and should not
be used to drive any load other than the delay line input.
Dimensions in Inches (mm)
TEST CONDITIONS -- FAST / TTL
V_CC Supply Voltage ............................................... 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25^OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output.
.020
(0.51)
TYP.
.810
(20.57)
MAX.
.260 .300
(6.60) ^(7.62)
TYP. ^MAX.
.120
(3.05)
MIN.
.050 .100
(1.27) (2.54)
TYP. TYP.
.400
(10.16)
MAX.
.010
(0.25)
TYP.
.300
(7.62)
OPERATING SPECIFICATIONS
V_CC Supply Voltage ................................... 5.00 ± 0.25 VDC
I_CC Supply Current .......................... 60 mA typ., 80 mA max
Logic “1” Input *: V_IH ..................... 2.00 V min., 5.50 V max.
I_IH ............................... 50 µA max. @ 2.70V
Logic “0” Input *: V_IL ....................................... 0.80 V max.
I_IL ............................................ -0.6 mA mA
V_OH Logic “1” Voltage Out ................................... 2.40 V min.
V_OL Logic “0” Voltage Out ................................ 0.50 V max.
P_WI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ......................... -0^O to +70^OC
Storage Temperature Range ...................... -65^O to +150^OC
* Refer to "INPUT FAN-IN" note above.
IIL/IIH specified for Programming pins 9, 10 & 11.
16-Pin SMD Pkg. Unused leads are NOT removed.
To Specify SMD Package, Add "G" Suffix to P/N
Examples: PLDM4-1.25G, PLDM4-2G
1.02
(25.9)
MAX.
.020
(0.51)
TYP.
.040
(1.02)
TYP.
.100
(2.54)
TYP.
.400
(10.16)
.285
(7.24)
MAX.
.015
(0.38)
.025
(0.64)
.510 (12.95)
.480 (12.19)
.010
(0.25)
TYP.
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PLDM4-G 2001-01