LVITD-12 Datasheet, PDF (1/1 Pages) Rhombus Industries Inc. – LVITD Series LVC Low Voltage Logic 10-Tap Delay Modules

LVITD Series LVC Low Voltage Logic 10-Tap Delay Modules
Inputs accept voltages up to 5.5 V
74LVC type input can be driven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
LVITD Schematic
Vcc Tap1 Tap3 Tap5 Tap7 Tap9 Tap10
14 13 12 11 10 9
8
Operating Temp. -40^OC to +85^OC
Low Profile 14-Pin Package
Two Surface Mount Versions
For 5-Tap 8-Pin Versions see LVMDM Series
1
23
4
5
6
7
IN N/C Tap2 Tap4 Tap6 Tap8 GND
Electrical Specifications at 25^OC
LVC Logic
10 Tap P/N
Tap 1
Tap 2
LVITD-12
3
4
LVITD-21
3
5
LVITD-30
3
6
LVITD-50
5
10
LVITD-60
6
12
LVITD-75
7.5
15
LVITD-80
8
16
LVITD-100
10
20
LVITD-125
12.5
25
LVITD-150
15
30
Tap Delay Tolerances +/- 5% or 2ns (>15ns +/- 1.0ns)
Tap 3 Tap 4 Tap 5 Tap 6 Tap 7 Tap 8 Tap 9
5
6
7
8
9
10
11
7
9
11
13
15
17
19
9
12
15
18
21
24
27
15
20
25
30
35
40
45
18
24
30
36
42
48
54
22.5
30
37.5
45
52.5
60
67.5
24
32
40
48
56
64
72
30
40
50
60
70
80
90
37.5
50
62.5
75
87.5 100 112.5
45
60
75
90
105
120
135
Total - Tap 10
12 ± 2.5
21 ± 2.5
30 ± 2.5
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
125 ± 6.25
150 ± 7.5
Tap-to-Tap
(ns)
1.0 ± 0.4
2.0 ± 0.6
3.0 ± 0.8
5.0 ± 1.8
6.0 ± 2.0
7.5 ± 2.0
8.0 ± 2.0
10.0 ± 2.0
12.5 ± 3.0
15.0 ± 3.0
TEST CONDITIONS -- Low Voltage CMOS, LVC
V_CC Supply Voltage ................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25^OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 50pf probe and fixture load on output under test.
OPERATING SPECIFICATIONS
Supply Voltage, V_CC .......................................... 3.3 ± 0.3 VDC
Supply Current, I_CC ........................... 10 mA typ., 30 mA max.
Supply Current, I_CCL : V_IN = GND ......................... 22 mA max.
Supply Current, I_CCH : V_IN = V_CC ............................. 10 µA max.
Input Voltage, V_I ..................................... 0 V min., 5.5 V max.
Logic “1” Input, V_IH .................................................. 2.0 V min.
Logic “0” Input, V_IL ................................................. 0.8 V max.
Logic “1” Out, V_OH: V_CC = 3V & I_OH = -24 mA ............ 2.0 V min.
Logic “0” Out, V_OL: V_CC = 3V & I_OL = 24 mA ......... 0.55 V max.
Input Capacitance, C_I ............................................. 5 pF, typ.
Input Pulse Width, P_WI .............................. 40% of Delay min.
Operating Temperature Range ......................... -40^O to +85^OC
Storage Temperature Range ........................ -65^O to +150^OC
.020
(0.51)
TYP.
.020
(0.51)
TYP.
P/N Description
LVITD - XXX X
LVC Buffered 10 Tap Delay
Molded Package Series:
14-pin DIP: LVITD
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
.020
(0.51)
TYP.
Examples: LVITD-30G = 30ns (3ns per tap) 74LVC, 14-Pin G-SMD
LVITD-100 = 100ns (10ns per tap) 74LVC, 14-Pin DIP
Dimensions in Inches (mm)
.785
(19.94)
MAX.
DIP
.050
(1.27)
TYP.
.020
.250
(6.35)
(0.51) _MAX.
.120
(3.05)
MIN.
.100
(2.54)
TYP.
.285
(7.24)
MAX.
DIP
.300
(7.62)
.365
(9.27)
MAX.
.008 R
(0.20)
.010
(0.25)
TYP.
.785
(19.94)
MAX.
G-SMD
.050
(1.27)
TYP.
.785
(19.94)
MAX.
J-SMD
.050
(1.27)
TYP.
.285
(7.24)
MAX.
.250
(6.35)
MAX.
.100
(2.54)
TYP.
.015
(0.38)
TYP.
.030
(0.76)
TYP.
G-SMD
.430 (10.92)
.400 (10.16)
.008 R
(0.20)
.010
(0.25)
TYP.
.285
(7.24)
MAX.
.265
(6.73)
MAX.
.100
(2.54)
TYP.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
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LVITD 2001-01