DAIDM-7 Datasheet, PDF (1/1 Pages) Rhombus Industries Inc. – DAIDM Series FAST / TTL Buffered 5-Tap Dual Edge Delay Modules

DAIDM Series FAST / TTL Buffered 5-Tap Dual Edge Delay Modules
Low Profile 14-Pin Package
Two Surface Mount Versions
8-Pin Versions: FAMDM Series
SIP Versions: FSIDM Series
FAST/TTL Logic Buffered
5 Equal Delay Taps
Low Voltage CMOS Versions
refer to LVMDM / LVIDM Series
Operating Temperature
Range 0^OC to +70^OC
DAIDM 14-Pin Schematic
Vcc
Tap1
Tap3
Tap5
14
12
10
8
Electrical Specifications at 25^OC
Dual Edge
14-Pin DIP P/N
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
Tap-to-Tap
(ns)
DAIDM-7
3.0
4.0
5.0
6.0
7 ± 1.0
∗∗ 1 ± 0.5
DAIDM-9
3.0
4.5
6.0
7.5
9 ± 1.0 ∗∗ 1.5 ± 0.5
DAIDM-11
3.0
5.0
7.0
9.0
11 ± 1.0
∗∗ 2 ± 0.7
DAIDM-13
3.0
5.5
8.0
10.5
13 ± 1.5 ∗∗ 2.5 ± 1.0
DAIDM-15
3.0
6.0
9.0
12.0
15 ± 1.5
3 ± 1.0
DAIDM-20
4.0
8.0
12.0
16.0
20 ± 2.0
4 ± 1.5
DAIDM-25
5.0
10.0
15.0
20.0
25 ± 2.0
5 ± 2.0
DAIDM-30
6.0
12.0
18.0
24.0
30 ± 2.0
6 ± 2.0
DAIDM-35
7.0
14.0
21.0
28.0
35 ± 2.0
7 ± 2.0
DAIDM-40
8.0
16.0
24.0
32.0
40 ± 2.0
8 ± 2.0
DAIDM-50
10.0
20.0
30.0
40.0
50 ± 2.5
10 ± 2.0
DAIDM-60
12.0
24.0
36.0
48.0
60 ± 3.0
12 ± 2.0
DAIDM-75
15.0
30.0
45.0
60.0
75 ± 3.75
15 ± 2.5
DAIDM-100
20.0
40.0
60.0
80.0
100 ± 5.0
20 ± 3.0
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
1
4
6
7
IN
Tap2
Tap4 GND
TEST CONDITIONS -- FAST / TTL
V_CC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25^OC
2. Delays measured at 1.50V level of leading & trailing edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output under test.
OPERATING SPECIFICATIONS
V_CC Supply Voltage ................................... 5.00 ± 0.25 VDC
I_CC Supply Current .................................... 48 mA Maximum
Logic “1” Input: V_IH ....................... 2.00 V min., 5.50 V max.
I_IH ............................... 20 µA max. @ 2.70V
Logic “0” Input: V_IL .......................................... 0.80 V max.
I_IL ............................................ -0.6 mA mA
V_OH Logic “1” Voltage Out .................................. 2.40 V min.
V_OL Logic “0” Voltage Out ............................... 0.50 V max.
P_WI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ............................ 0^O to 70^OC
Storage Temperature Range ...................... -65^O to +150^OC
.020
(0.51)
TYP.
DImensions in Inches (mm)
.785
(19.94)
MAX.
DIP
.050
(1.27)
TYP.
.020
.250
(6.35)
(0.51) _MAX.
.120
(3.05)
MIN.
.100
(2.54)
TYP.
.285
(7.24)
MAX.
DIP
.300
(7.62)
.365
(9.27)
MAX.
.008 R
(0.20)
.010
(0.25)
TYP.
.020
(0.51)
TYP.
.785
(19.94)
MAX.
G-SMD
.050
(1.27)
TYP.
.250
(6.35)
MAX.
.100
(2.54)
TYP.
.015 .030
(0.38) (0.76)
TYP. TYP.
.285
(7.24)
MAX.
G-SMD
.430 (10.92)
.400 (10.16)
.008 R
(0.20)
.010
(0.25)
TYP.
P/N Description
DAIDM - XXX X
Dual Edge Controlled
Buffered 5 Tap Delay
Molded Package Series:
14-pin DIP: DAIDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
.020
(0.51)
TYP.
.785
(19.94)
MAX.
J-SMD
.050
(1.27)
TYP.
.265
(6.73)
MAX.
.100
(2.54)
TYP.
.030
(0.76)
TYP.
.285
(7.24)
MAX.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
Examples: DAIDM-25G = 25ns (5ns per tap)
74F, 14-Pin G-SMD
DAIDM-100 = 100ns (20ns per tap)
74F, 14-Pin DIP
Specifications subject to change without notice.
For other values & Custom Designs, contact factory.
DAIDM 9901
Rhombus
Industries Inc.
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Phone: [phone] • FAX: [phone]
www.rhombus-ind.com • email: [e-mail]