ACMDM-30 Datasheet, PDF (1/1 Pages) Rhombus Industries Inc. – ACMDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules

ACMDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules
74ACT type input is compatible with TTL Outputs can Source / Sink 24 mA
Low Profile 8-Pin Package
Two Surface Mount Versions
Available in Low Voltage CMOS
74LVC Logic version LVMDM Series
5 Equal Delay Taps
Operating Temp. -40^OC to +85^OC
ACMDM 8-Pin Schematic
Vcc Tap1 Tap3 Tap5
8
7
6
5
Electrical Specifications at 25^OC
74ACT 5 Tap
8-Pin DIP P/N
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
ACMDM-30
6.0
ACMDM-35
7.0
ACMDM-40
8.0
ACMDM-50
10.0
ACMDM-60
12.0
ACMDM-75
15.0
ACMDM-80
16.0
ACMDM-100 20.0
ACMDM-125 25.0
ACMDM-150 30.0
ACMDM-200 40.0
ACMDM-250 50.0
12.0
14.0
16.0
20.0
24.0
30.0
32.0
40.0
50.0
60.0
80.0
100.0
18.0
21.0
24.0
30.0
36.0
45.0
48.0
60.0
75.0
90.0
120.0
150.0
24.0
28.0
32.0
40.0
48.0
60.0
64.0
80.0
100.0
120.0
160.0
200.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
Tap-to-Tap
(ns)
6 ± 2.0
7 ± 2.0
8 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
16 ± 3.0
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
1
23
4
IN Tap2 Tap4 GND
TEST CONDITIONS -- Advanced CMOS, 74ACT
V_CC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.00V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25^OC
2. Delay Times measured at 1.50V level of input to
+2.50V level of Output on leading edge.
3. Rise Times measured from 10% to 90% points.
4. 50pf probe and fixture load on output under test.
OPERATING SPECIFICATIONS
Supply Voltage, V_CC ...................................... 5.00 ± 0.50 VDC
Supply Current, I_CC ........................... 14 mA typ., 28 mA max.
I_CCH, V_IN = V_CC, V_CC = 5.5V ............................. 40 µA typ.
I_CCL, V_IN = 0V, V_CC = 5.5V ............................. 25 mA typ.
Logic “1” Input: V_IH ........................... 2.00 V min., 5.50V max.
Logic “0” Input: V_IL .............................................. 0.80 V max.
Logic “1” Voltage Out, V_OH ...................................... 3.8 V min.
Logic “0” Voltage Out, V_OL ................................... 0.44 V max.
Max. Input Current, I_IN ................................................ ± 1.0 µA
Minimum Input Pulse Width ........................ 40% of Delay min.
Operating Temperature Range ......................... -40^O to +85^OC
Storage Temperature Range ......................... -65^O to +150^OC
P/N Description
ACMDM - XXX X
74ACT Buffered 5 Tap Delay
Molded Package Series:
8-pin DIP: ACMDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
Examples: ACMDM-25G = 25ns (5ns per tap) 74ACT, 8-Pin G-SMD
ACMDM-100 = 100ns (20ns per tap) 74ACT, 8-Pin DIP
Dimensions in Inches (mm)
.505
(12.83)
MAX.
.285
(7.24)
MAX.
DIP
.020
(0.51)
TYP.
.250
(6.35)
MAX.
DIP
.020 .050 .100
(0.51) (1.27) (2.54)
TYP. TYP. TYP.
.120
(3.05)
MIN.
.300
(7.62)
.365
(9.27)
MAX.
.010
(0.25)
TYP.
.505
(12.83)
MAX.
.285
(7.24)
MAX.
G-SMD
.250
(6.35)
MAX.
.020 .050 .100
(0.51) (1.27) (2.54)
TYP. TYP. TYP.
.015
(0.38)
TYP.
G-SMD
.030
(0.76)
TYP.
.430 (10.92)
.400 (10.16)
.008 R
(0.20)
.010
(0.25)
TYP.
.505
(12.83)
MAX.
J-SMD
.265
(6.73)
MAX.
.020 .050 .100
(0.51) (1.27) (2.54)
TYP. TYP. TYP.
.030
(0.76)
TYP.
.285
(7.24)
MAX.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH
www.rhombus-ind.com
UKRPEXV LQGXVWULHV LQF
)RU RWKHU YDOXHV &XVWRP 'HVLJQV FRQWDFW IDFWRU\
[e-mail]
TEL: [phone]
17
FAX: [phone]
ACMDM 2001-01