RFSA2524 Datasheet, PDF (8/13 Pages) RF Micro Devices – SERIAL CONTROLLED DIGITAL STEP ATTENUATOR 50MHz TO 4000MHz, 5-BIT, 1dB LSB

RFSA2524
t4
CLK
DATA
t7
LE
DOUT
SPI Timing Diagram
t6
t1
t2
t3
t5
Serial Port Interface
t8
CLK
Programming Example - 5-Bit
DATA
MSB
LSB
D4 D3
D2
D1
D0
LE
t9
t10
Truth Table
Control Bits
C16
C8
C4
C2
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
0
0
Relative Gain
C1
Setting
1
Max gain
0
-1dB
1
-2dB
1
-4dB
1
-8dB
1
-16dB
0
-31dB
SPI Timing Diagram Specifications
Parameter
t1
Limit
25
Unit
MHz max
Comment
CLK Frequency
t2
20
ns min
CLK High
t3
20
ns min
CLK Low
t4
5
ns min
DATA to CLK Setup Time
t5
5
ns min
DATA to CLK Hold Time
t6
30
ns min
Data Valid
t7
5
ns min
LE to CLK Setup Time
t8
5
ns min
CLK to LE Setup Time
t9
10
ns min
LE Pulse Width
t10
20
ns max
Output Set
Logic Voltage Levels
State
Logic
Low
0V to 0.8V
High
2.0V to 5.0V
Power-up Programming Truth Table
PUP
Attenuator Setting
Low
Attenuation at max, 31dB
High
Attenuation at min, 0dB
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