TRC102 Datasheet, PDF (9/40 Pages) RF Monolithics, Inc – 400-1000MHz RF Transceiver

byte character uses only SB0, which is user configurable. A word character uses both SB1 and SB0 with
the lower byte SB0 being user configurable. This becomes an advantage when operating near other
interferers or identifying specific transmitters.
Automatic Frequency Adjustment (AFA)
The PLL has the capability to do fine adjustment of the carrier frequency automatically. In this way, the
receiver can minimize the offset between transmit and receive frequency. This function may be enabled
or disabled through the Automatic Frequency Adjustment Register. The range of offset can be
programmed as well as the offset value calculated and added to the frequency control word within the
PLL to incrementally change the carrier frequency. The chip can be programmed to automatically
perform an adjustment or may be manually activated by a strobe signal. This function has the advantage
of allowing:
• Low cost, lower accuracy crystals to be used
• Increased receiver sensitivity by narrowing the receive bandwidth
• Achieving higher data rates
Crystal Oscillator
The TRC102 incorporates an internal crystal oscillator circuit that provides a 10MHz reference, as well as
internal load capacitors. This significantly reduces the component count required. The internal load
capacitance is programmable from 8.5pF to 16pF in 0.5pF steps. This has the advantage of accepting a
wide range of crystals from many different manufacturers having different load capacitance requirements.
Being able to vary the load capacitance also helps with fine tuning the final carrier frequency since the
crystal is the PLL reference for the carrier. The crystal oscillator circuit is sensitive to parasitic
capacitance for startup. Only a slight amount of parasitic capacitance is needed to facilitate oscillation. A
recommended solution is to apply a ground plane around the crystal and widen the connection to the
TRC102. If this is not possible, a 0.5-1pF capacitor soldered across the crystal will initiate startup.
An external clock signal is also provided that may be used to run an external processor. This also has
the advantage of reducing component count by eliminating an additional crystal for the host processor.
The clock frequency is also programmable from eight pre-defined frequencies, each a pre-scaled value of
the 10MHz crystal reference. These values are programmable through the Battery Detect Threshold and
Clock Output Register. The internal clock oscillator may be disabled which also disables the output clock
signal to the host processor. When the oscillator is disabled, the chip provides an additional 196 clock
cycles before releasing the output, which may be used by the host processor to setup any functions
before going to sleep.
Frequency Control (PLL) and Frequency Synthesizer
The PLL synthesizer is the heart of the operating frequency. It is programmable and completely
integrated, providing all functions required to generate the carriers and tunability for each band. The PLL
requires only a single 10MHz crystal reference source. RF stability is controlled by choosing a crystal
with the particular specifications to satisfy the application. This gives the designer the maximum flexibility
in performance.
The PLL is able to perform manual and automatic calibration to compensate for changes in temperature
or operating voltage. When changing band frequencies, re-calibration must be performed. This can be
done by disabling the synthesizer and re-enabling again through the Power Management Register.
Registers common to the PLL are:
• Power Management Register
• Configuration Register
• Frequency Setting Register
• Automatic Frequency Adjust Register
• Transmit Configuration Register
Data Quality Detector (DQD)
The DQD is a unique function of the TRC102. The DQD circuit looks at the prefiltered incoming data and
counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link.
This parameter is programmable through the Data Filter Command Register. The DQD count threshold is
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