TRC103 Datasheet, PDF (6/65 Pages) RF Monolithics, Inc – 863-960 MHz RF Transceiver

 A two-stage IF filter followed by an amplifier chain for both the I and Q channels. Limiters at the end of
each chain drive the I and Q inputs to the FSK demodulator function. An RSSI signal is also derived from
the I and Q IF amplifiers to drive the OOK detector. The second filter stage in each channel can be con-
figured as either a third-order Butterworth low-pass filter for FSK operation or an image reject polyphase
band-pass filter for OOK operation.
 An FSK arctangent type demodulator driven from the I and Q limiter outputs, and an OOK demodulator
driven by the RSSI signal. Either detector can drive a data and clock recovery function that provides
matched filter enhancement of the demodulated data.
The transmitter chain is based on the same double-conversion architecture and uses the same intermediate fre-
quencies as the receiver chain. The main blocks include:
 A digital waveform generator that provides the I and Q base-band signals. This block includes digital-to-
analog converters and anti-aliasing low-pass filters.
 A compound image-rejection mixer to up convert the base-band signal to the first IF at 1/9th of the carrier
frequency, and a second image-rejection mixer to up-convert the IF signal to the RF frequency
 Transmitter driver and power amplifier stages to drive the antenna port
The frequency synthesizer is based on an integer-N PLL having a typical frequency step size of 12.5 kHz. Two
programmable frequency dividers in the feedback loop of the PLL and one programmable divider on the reference
oscillator allow the LO frequency to be adjusted. The reference frequency is generated by a crystal oscillator run-
ning at 12.8 MHz.
The TRC103 is controlled by a digital block that includes registers to store the configuration settings of the radio.
These registers are accessed by a host microcontroller through an SPI style serial interface. The microcontroller’s
serial connections to the TRC103’s SDI, SDO and SCK pins are shown in Figure 2 (component values shown are
for 950-960 MHz operation; see Tables 53 and 54 for other frequency bands). On-chip regulators provide stable
supply voltages to sensitive blocks and allow the TRC103 to be used with supply voltages from 2.1 to 3.6 V. Most
blocks are supplied with a voltage below 1.6 V.
C17
1.5 pF
C16
DNP
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Figure 2
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TRC103 - 10/16/12