OP4008B Datasheet, PDF (3/5 Pages) RF Monolithics, Inc – Quartz SAW Stabilized and Filtered “Diff Sine” Technology

669.327 MHz
Optical Timing Clock
Load Recommendations for the OP4008B
The Q and Q outputs of RFM's OPB-series of SAW
clocks are AC-coupled internally. This allows customers
to set the DC level of the outputs with a simple resistor
pair on each output to drive most any application.
1)
Vdc=
V _load x R1
R1 + R2
1+1=1
2) _{R1 R2 50}
Vdc is the DC level desired on the outputs.
V_load is the DC supply on the load resistors (typically 3.3 V).
3.3V
V_LOAD
V_TUNE
OP4005B
R2
R2
V _DC
V _DC
Load
R1
R1
Equations 1 & 2 describe the voltage divider created by R1 & R2 and the equilivent load impedence set by the parrellel com-
bination of R1 & R2.
A given load type will have specifications that set Vdc. Choose an available V_load that is 2x to 3x larger than the desired Vdc.
This will allow R1 to be expressed in terms of R2 as in equation 1. By substituting this result in equation 2, a value for R2
will result. Solving equation 1 for R1 with the known R2 is the last step.
Table 1 has some typical values for Vdc & V_load for various ECL loads along with R1 & R2 values that are standard.
Note that the OPB parts will drive negative ECL loads by applying negative voltage to the V_load points in the circuit.
Load Type
10k 3.3 V PECL
100k 3.3 V PECL
10k 5 V PECL
100k 5 V PECL
10k -5 V NECL
100k -5 V NECL
Vdc
R1
1.95
120
1.88
120
3.65
180
3.58
180
-1.30
240
-1.42
240
R2
V_load
91
3.3 V
91
3.3 V
68
5.0 V
68
5.0 V
62
-5.0 V
62
-5.0 V
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OP4008B-041003
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