DR3102 Datasheet, PDF (3/5 Pages) RF Monolithics, Inc – 418.00 MHz Transceiver Module

Pin Descriptions
Pin
Name
Description
This pin is connected directly to the transceiver AGCCAP pin. To disable AGC operation, this pin is tied to VCC.
To enable AGC operation, a capacitor is placed between this pin and ground. This pin controls the AGC reset op-
eration. A capacitor between this pin and ground sets the minimum time the AGC will hold-in once it is engaged.
The hold-in time is set to avoid AGC chattering. For a given hold-in time t_AGH, the capacitor value C_AGC is:
C_AGC = 19.1* t_AGH, where t_AGH is in µs and C_AGC is in pF
A ±10% ceramic capacitor should be used at this pin. The value of C_AGC given above provides a hold-in time be-
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AGC/VCC
tween t_AGH and 2.65* t_AGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow
the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in
time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time
should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by
noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs.
Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The
AGC can be latched ON once engaged by connecting a 150 K resistor between this pin and ground, instead of a
capacitor. AGC operation depends on a functioning peak detector, as discussed below. The AGC capacitor is dis-
charged in the transceiver power-down (sleep) mode and in the transmit modes. Note that provisions are made on
the circuit board to install a jumper between this pin and the junction of C2 and L3. Installing the jumper allows ei-
ther this pin or Pin 7 to be used for the Vcc supply when AGC operation is not required.
This pin is connected directly to the transceiver PKDET pin. This pin controls the peak detector operation. A ca-
pacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ra-
tio. For most applications, the attack time constant should be set to 6.4 ms with a 0.027 µF capacitor to ground.
(This matches the peak detector decay time constant to the time constant of the 0.1 µF coupling capacitor C3.) A
±10% ceramic capacitor should be used at this pin. The peak detector is used to drive the “dB-below-peak” data
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PK DET slicer and the AGC release function. The AGC hold-in time can be extended beyond the peak detector decay time
with the AGC capacitor, as discussed above. Where low data rates and OOK modulation are used, the
“dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin can be left unconnected, and
the AGC pin can be connected to VCC to reduce the number of external components needed. The peak detector
capacitor is discharged in the transceiver power-down (sleep) mode and in the transmit modes. See the descrip-
tion of Pin 3 below for further information.
This pin is connected directly to the transceiver BBOUT pin. On the circuit board, BBOUT also drives the trans-
ceiver CMPIN pin through C3, a 0.1 µF coupling capacitor (t_BBC = 6.4 ms). RX BBO can also be used to drive an
external data recovery process (DSP, etc.). The nominal output impedance of this pin is 1 K. The RX BBO signal
changes about 10 mV/dB, with a peak-to-peak signal level of up to 675 mV. The signal at RX BBO is riding on a
1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca-
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RX BBO pacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recom-
mended. Note the AGC reset function is driven by the signal applied to CMPIN through C3. When the transceiver
is in power-down (sleep) or in a transmit mode, the output impedance of this pin becomes very high, preserving
the charge on the coupling capacitor(s). The value of C3 on the circuit board has been chosen to match typical
data encoding schemes at 2.4 kbps. If C3 is modified to support higher data rates and/or different data encoding
schemes and PK DET is being used, make the value of the peak detector capacitor about 1/3 the value of C3.
RX DATA is connected directly to the transceiver data output pin, RXDATA. This pin will drive a 10 pF, 500 K par-
allel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In
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RX DATA
the power-down (sleep) or transmit modes, this pin becomes high impedance. If required, a 1000 K pull-up or
pull-down resistor can be used to establish a definite logic state when this pin is high impedance (do not connect
the pull-up resistor to a supply voltage higher than 3.5 Vdc or the transceiver will be damaged). This pin must be
buffered to successfully drive low-impedance loads.
The TX IN pin is connected to the transceiver TXMOD pin through a 4.7 K resistor on the circuit board. Additional
series resistance will often be required between the modulation source and the TX IN pin, depending on the de-
sired output power and peak modulation voltage (4.3 K typical for a peak modulation voltage of 3 volts). Saturated
output power requires about 250 µA of drive current. Peak output power P_O for a 3 Vdc supply is approximately:
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TX IN
P_O = 19.75*((V_TXH – 1.05)/(R_M + 4.7))², where P_O is in mW, peak modulation voltage V_TXH is in volts and
external modulation resistor R_M is in kilohms
This pin must be held low in the receive and sleep modes. Please refer to section 2.9 of the ASH Transceiver De-
signer’s Guide for additional information.
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