TXC102 Datasheet, PDF (23/30 Pages) RF Monolithics, Inc – Multi-channel High tae rate Programmable

Sleep/Clock Command Register [POR=C400h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
1
0
0 SLP7 SLP6 SLP5 SLP4 SLP3 SLP2 SLP1 SLP0
The Sleep Command Register defines the byte command and the number of clock cycles to generate after a sleep instruction to put
the chip into sleep mode. When the chip sees this command issued, it immediately disables the power amplifier, turns off the
synthesizer, and turns off the oscillator after SLP[7..0] clock cycles.
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Sleep Command Register.
Bit [7..0] – Sleep Command Value: These bits define the sleep command value that is issued by a host controller instructing the
chip to go into sleep mode. This also sets the number of clock cycles that are generated after the oscillator has been
disabled and before the chip goes into sleep mode.
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