OP4006B1 Datasheet, PDF (1/2 Pages) RF Monolithics, Inc – 666.51 MHz Optical Timing Clock

Preliminary
®
• Quartz SAW Stabilized Differential Output Technology
• Very Low Jitter Fundamental-Mode Operation at 666.51 MHz
• Voltage Tunable for Phase Locked Loop Applications
• Optical Timing Reference for Forward Error Correction Applications
The OP4006B1 is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications
in optical data communications systems. The differential outputs of the OP4006B1 are generated by high-Q,
fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output
jitter and phase noise, plus excellent immunity to power supply noise. The OP4006B1 differential outputs fea-
ture ±1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The
OP4006B1 is packaged in a hermetic metal-ceramic LCC.
Absolute Maximum Ratings
Rating
DC Suppy Voltage
Tune Voltage
Case Temperature
Value
0 to 5.5
0 to 5.5
-55 to 100
Units
Vdc
Vdc
°C
OP4006B1
666.51 MHz
Optical
Timing Clock
SMC-08A
Electrical Characteristics
Characteristic
Operating Frequency Absolute Frequency
Tuning Range
Tuning Voltage
Tuning Linearity
Modulation Bandwidth
Q and Q Output
Voltage into 50 Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Phase Noise
@ 100 Hz offset
@ 1 kHz offset
@ 10 kHz offset
Noise Floor
Q and Q Jitter
RMS Jitter
No Noise on V_CC
200 mV_P-P Noise, from 1 MHz to ½ f_O on V_CC
Output DC Resistance (between Q & Q)
DC Power Supply
Operating Voltage
Operating Current
Operating Case Temperature
Lid Symbolization (YY=Year, WW=Week)
Sym
f_O
V_O
V_CC
I_CC
T_C
Notes
1
2
1
1, 8
1,3
1,3
3, 4, 5
3, 4, 6
3, 4, 6, 7
3, 6
3, 6
3, 6
3, 6
3, 4, 6, 7
3, 4, 6, 7
3
1, 3
1, 3
1, 3
1, 3
Minimum
0
0.60
Typical
666.51
±100
±5
50
49
-70
-100
-125
-150
1
12
12
50
3.13
3.3 or 5.0
-40°C
RFM OP4006B1 YYWW
Maximum
3.3
1.1
2:1
51
-15
-60
5.25
70
+85°C
Units
MHz
ppm
Vdc
%
kHz
V_P-P
%
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps_P-P
ps_P-P
KΩ
Vdc
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. COCOM CAUTION: Approval by the U.S. Department of Commerce is required
prior to export of this device.
Notes:
1. Unless otherwise noted, all specifications include the combined effects of load VSWR, V_CC and T_C.
2. Net tuning range after tuning out the effects of initial manufacturing tolerances, VSWR pushing/pulling, V_CC, T_C and aging.
3. The internal design, manufacturing processes, and specifications of this device are subject to change without notice.
4. Specified only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a V_CC = 3.0 Vdc.
5. Symmetry is defined as the width in (% of total period) measure at 50% of the peak-to-peak voltage of either output.
6. Jitter and other noise outputs due to power supply noise or mechanical vibration are not included in this specification except where noted.
7. Applies to period jitter of either differential output. Measured with a Tektronix CSA803 signal analyzer with at least 1000 samples.
8. See Figure 4.
9. One or more of the following United States patents apply: 4, 616,197; 4,670,681; 4,760,352.
RF Monolithics, Inc. Phone: [phone]
Fax: [phone]
RFM Europe
Phone: [phone]
Fax: [phone]
©2001 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: [e-mail]
http://www.rfm.com
OP4006B1-041003
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