OMAP-L137 Datasheet, PDF(97/219 Page) Texas Instruments

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OMAP-L137 Datasheet, PDF (97/219 Pages) Texas Instruments – Low-Power Applications Processor

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OMAP-L137 Low-Power Applications Processor

SPRS563A â SEPTEMBER 2008 â REVISED OCTOBER 2008

GPIO

BYTE ADDRESS

0x01E2 6028

0x01E2 602C

0x01E2 6030

0x01E2 6034

0x01E2 6038

0x01E2 603C

0x01E2 6040

0x01E2 6044

0x01E2 6048

0x01E2 604C

0x01E2 6050

0x01E2 6054

0x01E2 6058

0x01E2 605C

0x01E2 6060

0x01E2 6064

0x01E2 6068

0x01E2 606C

0x01E2 6070

0x01E2 6074

0x01E2 6078

0x01E2 607C

0x01E2 6080

0x01E2 6084

0x01E2 6088

0x01E2 608C

0x01E2 6090

0x01E2 6094

0x01E2 6098

0x01E2 609C

0x01E2 60A0

0x01E2 60A4

0x01E2 60A8

0x01E2 60AC

Table 6-8. GPIO Registers (continued)

Acronym

CLR_RIS_TRIG01

SET_FAL_TRIG01

CLR_FAL_TRIG01

INTSTAT01

DIR23

OUT_DATA23

SET_DATA23

CLR_DATA23

IN_DATA23

SET_RIS_TRIG23

CLR_RIS_TRIG23

SET_FAL_TRIG23

CLR_FAL_TRIG23

INTSTAT23

DIR45

OUT_DATA45

SET_DATA45

CLR_DATA45

IN_DATA45

SET_RIS_TRIG45

CLR_RIS_TRIG45

SET_FAL_TRIG45

CLR_FAL_TRIG45

INTSTAT45

DIR67

OUT_DATA67

SET_DATA67

CLR_DATA67

IN_DATA67

SET_RIS_TRIG67

CLR_RIS_TRIG67

SET_FAL_TRIG67

CLR_FAL_TRIG67

INTSTAT67

GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register

GPIO Banks 0 and 1 Set Falling Edge Interrupt Register

GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register

GPIO Banks 0 and 1 Interrupt Status Register

GPIO Banks 2 and 3

GPIO Banks 2 and 3 Direction Register

GPIO Banks 2 and 3 Output Data Register

GPIO Banks 2 and 3 Set Data Register

GPIO Banks 2 and 3 Clear Data Register

GPIO Banks 2 and 3 Input Data Register

GPIO Banks 2 and 3 Set Rising Edge Interrupt Register

GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register

GPIO Banks 2 and 3 Set Falling Edge Interrupt Register

GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register

GPIO Banks 2 and 3 Interrupt Status Register

GPIO Banks 4 and 5

GPIO Banks 4 and 5 Direction Register

GPIO Banks 4 and 5 Output Data Register

GPIO Banks 4 and 5 Set Data Register

GPIO Banks 4 and 5 Clear Data Register

GPIO Banks 4 and 5 Input Data Register

GPIO Banks 4 and 5 Set Rising Edge Interrupt Register

GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register

GPIO Banks 4 and 5 Set Falling Edge Interrupt Register

GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register

GPIO Banks 4 and 5 Interrupt Status Register

GPIO Banks 6 and 7

GPIO Banks 6 and 7 Direction Register

GPIO Banks 6 and 7 Output Data Register

GPIO Banks 6 and 7 Set Data Register

GPIO Banks 6 and 7 Clear Data Register

GPIO Banks 6 and 7 Input Data Register

GPIO Banks 6 and 7 Set Rising Edge Interrupt Register

GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register

GPIO Banks 6 and 7 Set Falling Edge Interrupt Register

GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register

GPIO Banks 6 and 7 Interrupt Status Register

6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing

Table 6-9. Timing Requirements for GPIO Inputs(1) (see Figure 6-9)

NO.

1 tw(GPIH)

Pulse duration, GPIx high

MIN MAX

2C (1) (2)

UNIT

(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have OMAP-L137

recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow OMAP-L137

enough time to access the GPIO register through the internal bus.

(2) C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns

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Peripheral Information and Electrical Specifications

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