H83028 Datasheet, PDF (909/923 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

P6₇/φ
Access to external
memory
T1 T2 T3
RES
Internal reset
signal
A₂₃ to A₀
High impedance
AS, RD
(read)
HWR, LWR
(write)
D₁₅ to D₀
(write)
I/O port,
CS₇ to CS₁
High impedance
High impedance
Figure D.3 Reset during Memory Access (Mode 5)
Modes 6 and 7: Figure D.4 is a timing diagram for the case in which RES goes low during an
operation in mode 6 or 7. As soon as RES goes low, all ports are initialized to the input state.
Clock pin P6₇/φ goes to the output state at the next rise of φ after RES goes low.
P6₇/φ
RES
Internal reset
signal
I/O port
High impedance
Figure D.4 Reset during Operation (Modes 6 and 7)
Rev. 2.00, 09/03, page 879 of 890