M30245 Datasheet, PDF (90/266 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30245 Group
Universal Serial Bus
USB Endpoint 0 WRT CNT Register
The USB Endpoint 0 WRT CNT Register, shown in Figure 1.57, contains the number of bytes of the current data set in
the OUT buffer. The USB FCU sets the value in the WRT_CNT Register after having successfully received a data set
from the host. The CPU reads the register to determine the number of bytes to be read from the buffer. The WRT_CNT
value does not decrement upon a CPU read from the FIFO Data Register. The WRT_CNT value is cleared when the
CPU writes a "1" to the CLR_OUT_BUF_RDY bit of the EP0 CSR.
USB Endpoint 0 Write Count register
(b15)
b7
(b8)
b0 b7
00000000
b0
Symbol
EP0WC
Bit Symbol
Address
029C₁₆
Bit Name
When reset
0000₁₆
Function
RW
EP0WC7-0
Reserved
Receive byte count
Must always be "0"
OX
OO
Figure 1.57. USB Endpoint 0 write count register (EP0WC)
USB Endpoint x IN CSR (x = 1 to 4)
The USB Endpoint x IN control status register, shown in Figure 1.58, contains control and status information of the
respective IN EP 1-4.
• INxCSR0 (IN_BUF_STS0) and INxCSR1 (IN_BUF_STS1):
Two status flags, indicate the current status of the IN buffer. These two flags are "1"s after reset, and become "0"s when
the respective endpoint is enabled from a disabled state. The buffer status flags get updated when one of the following
events occurs:
1. The USB FCU successfully sends out a data set to the host.
2. The CPU loads a data set to the buffer (writes a "1" to SET_IN_BUF_RDY).
3. The CPU writes a "1" to the FLUSH bit or a hardware auto flush takes place.
• INxCSR2 (UNDER_RUN):
A status flag, "1" indicates an under run has occurred in an isochronous data transfer. The USB FCU updates this flag
to a "1" at the beginning of an IN token if no data packet is in the buffer.
• INxCSR3 (SET_IN_BUF_RDY):
The CPU writes a "1" to this bit after loading a data set to the buffer. The CPU can only load data to the buffer and set this
bit when INxCSR1 (IN_BUF_STS1) is a "0".
• INxCSR4 (CLR_UNDER_RUN):
The CPU writes a "1" to this bit to clear the UNDER_RUN status flag.
• INxCSR5 (TOGGLE_INIT):
The CPU writes a "1" to this bit to initialize the data sequence, force the next packet’s data PID to a DATA0 for transmis-
sion. Setting the TOGGLE_INT bit also resets the FIFO read/write pointers.
• INxCSR5 (TOGGLE_INIT):
The CPU writes a "1" to this bit to initialize the data sequence, force the next packet’s data PID to a DATA0 for transmis-
sion. Setting the TOGGLE_INT bit also resets the FIFO read/write pointers.
Rev.2.00 Oct 16, 2006 page 90 of 264
REJ03B0005-0200