RD74LVC126B_15 Datasheet, PDF (9/11 Pages) Renesas Technology Corp – Quad. Bus Buffer Gates with 3-state Outputs

RD74LVC126B
Waveforms – 1
Input A
10 %
t_r
90 %
V_ref
t_PLH
t_f
90 %
V_ref
10 %
t_PHL
Output Y
V_ref
V_ref
Note: 1. Input waveform : PRR = 10 MHz, duty cycle 50%
V_IH
GND
V_OH
V_OL
Waveforms – 2
Input OE
t_r
10 %
90 %
V_ref
t_ZL
Waveform - A
V_ref
t_ZH
Waveform - B
V_ref
t_f
90 %
V_ref
10 %
t_LZ
t_HZ
V_OL + ∆V
V_OH – ∆V
V_IH
GND
≈ 1/2 V_TT
V_OL
V_OH
≈ GND
INPUTS
VCC (V)
VI
tr/tf
Vref VTT CL
RL ∆V
VCC = 1.8±0.15 V VCC ≤ 2 ns 1/2 VCC 2× VCC 30 pF 1.0 kΩ 0.15 V
VCC = 2.5±0.2 V VCC ≤ 2 ns 1/2 VCC 2× VCC 30 pF 500 Ω 0.15 V
VCC = 2.7 V
2.7 V ≤ 2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V
VCC = 3.3±0.3 V 2.7 V ≤ 2.5 ns 1.5 V 6 V 50 pF 500 Ω 0.3 V
VCC = 5.0±0.5 V VCC ≤ 2.5 ns 1/2 VCC 2× VCC 50 pF 500 Ω 0.3 V
Notes:
1. Input waveform : PRR = 10 MHz, duty cycle 50%
2. Waveform – A shows input conditions such that the output is "L" level when enable by the
output control.
3. Waveform – B shows input conditions such that the output is "H" level when enable by the
output control.
Rev.2.00 Dec. 10, 2004 page 7 of 8