R1QHA3636CBG Datasheet, PDF (9/38 Pages) Renesas Technology Corp – 36-Mbit DDRII+ SRAM 2-word Burst

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72M_36M
R1QHA36**CB* / R1QLA36**CB* Series
General Description
Power-up and Initialization Sequence
- V_DD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : V_SS ൺ V_DD ൺ V_DDQ & V_REF ൺ V_IN. (0 V to V_DD, V_DDQ < 200 ms)
- Apply V_REF after V_DDQ or at the same time as V_DDQ.
- Then execute either one of the following three sequences.
1. Single Clock Mode (C and /C tied high)
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series).
These meet the QDR common specification of 20 us.
1. Sin^Wgl^he^ecⁿlo^thc^ek^om^peo^rd^ae^tin(C^{g f}a^rn^eqd^u/^eC^ncp^yin^iss ^lf^eix^ssed^thH^anig¹h⁸)^{0 MHz, 2048 cycles are required (II series).}
Status
V_DD
V_DDQ
V_REF
/DOFF
K, /K
Power Up &
Unstable Stage
NOP &
Set-up Stage
Normal
Operation
Fix High (=Vddq)
SET-UP Cycle
2. Double Clock Mode (C and /C control outputs) (II series only)
- Drive /DOFF high (/DOFF can be tied high from the start)
- Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series).
This meets the QDR common specification of 20 us.
2. Do^Wub^hl^eeⁿc^tl^ho^eck^opm^ero^ad^tie^{ng frequency is less than 180 MHz, 2048 cycles are required (II series).}
Status
V_DD
V_DDQ
V_REF
/DOFF
K, /K
Power Up &
Unstable Stage
NOP &
Set-up Stage
Normal
Operation
Fix High (=Vddq)
SET-UP Cycle
C, /C
3. DLL/PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+
series). These meet the QDR common specification of 20 us.
Rev. 0.09a : 2011.09.14
R10DS0162EJ0009
PAGE : 9