HN58X2502IAG Datasheet, PDF (9/22 Pages) Renesas Technology Corp – Serial Peripheral Interface Electrically Erasable and Programmable Read Only Memory

HN58X2502IAG/HN58X2504IAG
Functional Description
Status Register
The following figure shows the Status Register Format. The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific instructions.
Status Register Format
b7
b0
1
1
1
1
BP1 BP0 WEL WIP
Block Protect Bits
Write Enable Latch Bits
Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be protected
against Write instructions.
Instructions
Each instruction starts with a single-byte code, as summarized in the following table . If an invalid instruction is sent
(one not contained in the following table), the device automatically deselects itself.
Instruction Set
Instruction
Description
Instruction Format
WREN
Write Enable
0000 ×110
WRDI
Write Disable
0000 ×100
RDSR
Read Status Register
0000 ×101
WRSR
Write Status Register
0000 ×001
READ
Read from Memory Array
0000 A011
WRITE
Write to Memory Array
0000 A010
Notes: 1. “×” is Don’t care.
2. “A” is A₈ address on the HN58X2504IAG, and Don’t care on the HN58X2502IAG.
Rev.1.00, Nov.16.2006, page 9 of 20