HD74LV126A_15 Datasheet, PDF (9/12 Pages) Renesas Technology Corp – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV126A
• Waveform − 1
Input A
Output Y
tr
10 %
90 %
50 %V_CC
t_PLH
tf
90 %
50 %V_CC
10 %
t_PHL
50 %V_CC
50 %V_CC
V_CC
GND
V_OH
V_OL
• Waveform − 2
Input OE
Waveform − A
Waveform − B
tr
10 %
90 %
50 %V_CC
t_ZL
50 %V_CC
t_ZH
tf
90 %
50 %V_CC
10 %
t_LZ
t_HZ
50 %V_CC
V_OL + 0.3 V
V_OH − 0.3 V
V_CC
GND
V_CC
V_OL
V_OH
GND
Notes:
1. t_r ≤ 3 ns, t_f ≤ 3 ns
2. Input waveform: PRR ≤ 1 MHz, duty cycle 50%
3. Waveform−A is for an output with internal conditions such that the output is low except when
disabled by the output control.
4. Waveform−B is for an output with internal conditions such that the output is high except when
disabled by the output control.
Rev.3.00 Jun. 03, 2004 page 7 of 9