HD74ALVC2G74_15 Datasheet, PDF (9/13 Pages) Renesas Technology Corp – Single D-type Flip Flops with Preset and Clear

HD74ALVC2G74
V_CC = 1.8±0.15 V
Item
Test
FROM TO
Symbol Min
Typ
Max
Unit conditions (Input) (Output)
Maximum clock f_max
frequency
160
350

MHz C_L = 30 pF
Propagation
t_PLH
delay time
t_PHL
1.5

1.5

8.0
ns
C_L = 30 pF PRE/CLR Q or Q
8.0
CLK
Setup time
t_su
3.5


ns
3.0


D
PRE or CLR inactive
Hold time
t_h
Pulse width
t_w
0.0


ns
2.5


ns
2.5


PRE or CLR “L”
CLK “H” or “L”
V_CC = 2.5±0.2 V
Item
Test
FROM TO
Symbol Min
Typ
Max
Unit conditions (Input) (Output)
Maximum clock f_max
frequency
160
400

MHz C_L = 30 pF
Propagation
t_PLH
delay time
t_PHL
1.0

1.0

5.0
ns
C_L = 30 pF PRE/CLR Q or Q
5.0
CLK
Setup time
t_su
2.5


ns
2.0


D
PRE or CLR inactive
Hold time
t_h
Pulse width
t_w
0.0


ns
2.0


ns
2.0


PRE or CLR “L”
CLK “H” or “L”
V_CC = 3.3±0.3 V
Item
Test
FROM TO
Symbol Min
Typ
Max
Unit conditions (Input) (Output)
Maximum clock f_max
frequency
200
450

MHz C_L = 30 pF
Propagation
t_PLH
delay time
t_PHL
1.0

1.0

3.5
ns
C_L = 30 pF PRE/CLR Q or Q
3.5
CLK
Setup time
t_su
2.0


ns
2.0


D
PRE or CLR inactive
Hold time
t_h
Pulse width
t_w
0.0


ns
2.0


ns
2.0


PRE or CLR “L”
CLK “H” or “L”
Rev.3.00, Dec.18.2003, page 7 of 10