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M3850 Datasheet, PDF (84/88 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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3850 Group (Spec.A)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
2. Notes when selecting clock asynchronous serial I/O (Serial I/O1)
(1) Stop of transmission operation
Clear the transmit enable bit to â0â (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to â0â
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
â1â at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to â0â (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to â0â (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to â0â
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
â1â at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to â0â (receive disabled).
3. Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to â0â.
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to â0â
â
Set the bits 0 to 3 and bit 6 of the serial I/O1
control register
â
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to â1â
Can be set with the
LDM instruction at
the same time
Fig. 6 Sequence of setting serial I/O1 control register again
4. Data transmission control with referring to transmit shift register
completion flag (Serial I/O1)
The transmit shift register completion flag changes from â1â to â0â
with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
5. Transmit interrupt request when transmit enable bit is set (Serial
I/O1)
When the transmit interrupt is used, set the transmit interrupt en-
able bit to transmit enabled as shown in the following sequence.
(1) Set the interrupt enable bit to â0â (disabled) with CLB instruction.
(2) Prepare serial I/O for transmission/reception.
(3) Set the interrupt request bit to â0â with CLB instruction after 1
or more instruction has been executed.
(4) Set the interrupt enable bit to â1â (enabled).
<Reason>
When the transmission enable bit is set to â1â, the transmit buffer
empty flag and transmit shift register completion flag are set to â1â.
The interrupt request is generated and the transmission interrupt
request bit is set regardless of which of the two timings listed be-
low is selected as the timing for the transmission interrupt to be
generated.
⢠Transmit buffer empty flag is set to â1â
⢠Transmit shift register completion flag is set to â1â
6. Transmission control when external clock is selected (Serial I/
O1 clock synchronous mode)
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to â1â at âHâ of the SCLK1
input level. Also, write the transmit data to the transmit buffer reg-
ister (serial I/O shift register) at âHâ of the SCLK1 input level.
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial
I/O2 register (serial I/O shift register) at âHâ of the transfer clock in-
put level.
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and âLâ
level is output from the PWM pin.
The length of this âLâ level output is as follows:
n+1
2 ⢠f(XIN)
n+1
f(XIN)
sec. (Count source selection bit = â0â,
where n is the value set in the prescaler)
sec. (Count source selection bit = â1â,
where n is the value set in the prescaler)
Rev.2.10 2005.11.14 page 84 of 86
REJ03B0093-0210
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