H8S2368 Datasheet, PDF (813/1037 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
voltage for more than the specified time will be applied and flash memory may be damaged.
Therefore, interrupts, movement of bus mastership to other than the CPU (DMAC, DTC, or
1set to B'1 in interrupt control mode 0 or bits 2 to 0 (I2 to I0) in the extend control register of
the CPU should be set to B'111 in interrupt control mode 2. Then interrupts other than NMI are
held and are not executed.
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed after all program processing.
When the bus mastership is moved to other than the CPU by the DMAC, DTC, or BREQ
signal or DRAM refresh cycles are entered, the error protection state is entered. Therefore,
taking bus mastership by the DMAC, DTC, or BREQ signal is prohibited.
10. FKEY must be set to H'5A and the user MAT must be prepared for programming.
11. The parameter which is required for programming is set.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
 Example of the FMPAR setting
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits (A7 to A0) must be H'00 or H'80 as the
boundary of 128 bytes.
 Example of the FMPDR setting
When the storage destination of the program data is flash memory, even if the program
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to the on-chip RAM
and then programming must be executed.
12. Programming
There is an entry point of the programming program in the area from the start address specified
by FTDAR + 16 bytes of the on-chip RAM. The subroutine is called and programming is
executed by using the following steps.
MOV.L
JSR
NOP
#DLTOP+16,ER2;
@ER2;
Set entry address to ER2
Call programming routine
 The general registers other than ER0, ER1 are held in the programming program.
 R0L is a return value of the FPFR parameter.
Rev. 5.00 Aug 02, 2006 page 759 of 980
REJ09B0050-0500