R5F64210JFB Datasheet, PDF (80/115 Pages) Renesas Technology Corp – 32M Synchronous Late Write Fast Static RAM (1-Mword × 36-bit)

Under development
R32C/121 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
5. Electrical Characteristics
Table 5.5
Operating Conditions (4)
(V_CC = 3.0 to 5.5 V, V_SS = 0 V, and T_a = T_opr, unless otherwise noted) ⁽¹⁾
Symbol
Characteristic
Value
Min. Typ.
f_(XIN)
f_(XRef)
f_(PLL)
f_(Base)
t_c(Base)
f_(CPU)
t_c(CPU)
Main clock oscillator frequency
Reference clock frequency
PLL clock oscillator frequency
Base clock frequency
Base clock cycle time
CPU operating frequency
CPU clock cycle time
4
2
96
15.625
15.625
f_(BCLK)
t_c(BCLK)
Peripheral bus clock operating frequency
Peripheral bus clock cycle time
31.25
f_(PER)
f_(XCIN)
Peripheral clock source frequency
Sub clock oscillator frequency
32.768
Note:
1. The device is operationally guaranteed under these operating conditions.
Max.
8
4
144
64
64
32
32
50
Unit
MHz
MHz
MHz
MHz
ns
MHz
ns
MHz
ns
MHz
kHz
Base clock
(Internal signal)
CPU clock
(Internal signal)
Peripheral bus clock
(Internal signal)
Figure 5.1 Clock Cycle Time
t _c(Base)
t _c(CPU)
t _c(BCLK)
REJ03B0237-0050 Rev.0.50 Jul 31, 2008
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