S13158EJ4V0DS00_15 Datasheet, PDF (8/22 Pages) Renesas Technology Corp – 5150 PIXELS CCD LINEAR IMAGE SENSOR

µ PD3737
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, fφ 1 = 0.5 MHz, data rate = 1 MHz, storage time = 10 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C500 (infrared cut filter, t = 1 mm)
Parameter
Saturation voltage
Saturation exposure
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
Response peak
Image lag
Offset level ^{Note 1}
Output fall delay time ^{Note 2}
Register imbalance
Total transfer efficiency
Dynamic range
Reset feed-through noise ^{Note 1}
Symbol
Test Conditions
Min.
Vsat
1.0
SE
Daylight color fluorescent lamp
−
PRNU
VOUT = 500 mV
−
ADS
Light shielding
−
DSNU Light shielding
−
PW
−
ZO
−
RF
Daylight color fluorescent lamp
6.0
−
IL
VOUT = 1.0 V
−
VOS
2.0
td
Time from 90% to 10% of φ 2L fall is 5 ns
21
RI
VOUT = 500 mV
−
TTE
VOUT = 500 mV,
92
data rate (fφ R1) = 20 MHz
DR1
Vsat/DSNU
−
RFTN
Light shielding
−
Typ.
1.5
0.2
±5
2.0
6.0
100
0.2
7.5
550
0.3
3.0
23
0
98
250
250
Max.
−
−
±10
6.0
12.0
200
0.5
9.0
−
1.0
5.0
25
4.0
−
Unit
V
lx•s
%
mV
mV
mW
kΩ
V/lx•s
nm
%
V
ns
%
%
−
times
500
mV
Notes 1. Refer to TIMING CHART 2.
2. td is defined as a time from 10% of φ 2L to 10% of VOUT, output after passing through two steps of emitter
follower in the APPLICATION CIRCUIT EXAMPLE.
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Symbol Pin name Pin No. Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
Cφ 1
φ1
24
440
550
660
pF
Shift register clock pin capacitance 2
Cφ 2
φ2
10
440
550
660
pF
Last stage shift register clock pin capacitance 1
Cφ 1L
φ 1L
22
40
50
60
pF
Last stage shift register clock pin capacitance 2
Cφ 2L
φ 2L
9
40
50
60
pF
Reset gate clock pin capacitance
Cφ R
φR
32
8
10
12
pF
Transfer gate clock pin capacitance
Cφ TG
φ TG
23
120
150
180
pF
Remark Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and φ 2.
6
Data Sheet S13158EJ4V0DS