R1LV3216R_15 Datasheet, PDF (8/20 Pages) Renesas Technology Corp – 32Mb Advanced LPSRAM (2M word x 16bit / 4M word x 8bit)

R1LV3216R Series
Read Cycle
Parameter
R1LV3216R**-5S R1LV3216R**-7S
Symbol
Unit
Min. Max. Min. Max.
Read cycle time
t_RC
55
-
70
-
ns
Address access time
t_AA
-
55
-
70
ns
Chip select access time
t_ACS1
-
55
-
70
ns
t_ACS2
-
55
-
70
ns
Output enable to output valid
t_OE
-
25
-
35
ns
Output hold from address change
t_OH
10
-
10
-
ns
LB#, UB# access time
t_BA
-
55
-
70
ns
Chip select to output in low-Z
t_CLZ1
10
-
10
-
ns
t_CLZ2
10
-
10
-
ns
LB#, UB# enable to low-Z
t_BLZ
5
-
5
-
ns
Output enable to output in low-Z
t_OLZ
5
-
5
-
ns
Chip deselect to output in high-Z
t_CHZ1
0
20
0
25
ns
t_CHZ2
0
20
0
25
ns
LB#, UB# disable to high-Z
t_BHZ
0
20
0
25
ns
Output disable to output in high-Z
t_OHZ
0
20
0
25
ns
Note
2,3
2,3
2,3
2,3
1,2,3
1,2,3
1,2,3
1,2,3
REJ03C0367-0100, Rev.1.00, 2009.05.07
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