R1LP0108E_13 Datasheet, PDF (8/14 Pages) Renesas Technology Corp – 1Mb Advanced LPSRAM (128k word x 8bit)

R1LP0108E Series
Read Cycle
Parameter
Read cycle time
Address access time
Chip select access time
Output enable to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Symbol
t_RC
t_AA
t_ACS1
t_ACS2
t_OE
t_OH
t_CLZ1
t_CLZ2
t_OLZ
t_CHZ1
t_CHZ2
t_OHZ
R1LP0108E**-5**
Min.
Max.
55
-
-
55
-
55
-
55
-
30
5
-
5
-
5
-
5
-
0
20
0
20
0
20
R1LP0108E**-7**
Unit
Note
Min.
Max.
70
-
ns
-
70
ns
-
70
ns
-
70
ns
-
35
ns
10
-
ns
10
-
ns
2,3
10
-
ns
2,3
5
-
ns
2,3
0
25
ns
1,2,3
0
25
ns
1,2,3
0
25
ns
1,2,3
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
Address setup time
Write recovery time
Data to write time overlap
Data hold from write time
Output enable from end of write
Output disable to output in high-Z
Write to output in high-Z
Symbol
t_WC
t_AW
t_CW
t_WP
t_AS
t_WR
t_DW
t_DH
t_OW
t_OHZ
t_WHZ
R1LP0108E**-5**
Min.
Max.
55
-
50
-
50
-
45
-
0
-
0
-
25
-
0
-
5
-
0
20
0
20
R1LP0108E**-7**
Min.
Max.
70
-
55
-
55
-
50
-
0
-
0
-
30
-
0
-
5
-
0
25
0
25
Unit
Note
ns
ns
ns
5
ns
4
ns
6
ns
7
ns
ns
ns
2
ns
1,2
ns
1,2
Note
1. t_CHZ, t_OHZ and t_WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t_HZ max is less than t_LZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#.
A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low.
A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high.
t_WP is measured from the beginning of write to the end of write.
5. t_CW is measured from the later of CS1# going low or CS2 going high to end of write.
6. t_AS is measured the address valid to the beginning of write.
7. t_WR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
8. Don’t apply inverted phase signal externally when DQ pin is output mode.
R10DS0151EJ0100 Rev.1.00
2013.6.21
Page 8 of 12